LT6203 LINER [Linear Technology], LT6203 Datasheet - Page 5

• Manufacturer Part Number: LT6203
• Description: 16-Bit, 2Msps, Pseudo-Differential Unipolar SAR
• Manufacturer: LINER [Linear Technology]

ADC TIMING CHARACTERISTICS
SYMBOL
t
t
t
t
t
t
t
t
t
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may effect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REF or
OV
input currents up to 100mA below ground or above REF or OV
latch-up.
Note 4: V
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
temperature range, otherwise specifications are at T
SCKL
SSDISCK
HSDISCK
SCKCH
DSDO
HSDO
DSDOBUSYL
EN
DIS
DD
, they will be clamped by internal diodes. This product can handle
DD
= 2.5V, OV
PARAMETER
SCK Low Time
SDI Setup Time From SCK↑
SDI Hold Time From SCK↑
SCK Period in Chain Mode
SDO Data Valid Delay from SCK↑
SDO Data Remains Valid Delay from SCK↑
SDO Data Valid Delay from BUSY↓
Bus Enable Time After RDL↓
Bus Relinquish Time After RDL↑
DD
= 2.5V, REF = 5V, f
0.8*OV
0.8*OV
0.2*OV
DD
t
DELAY
DD
DD
SMPL
Figure 1. Voltage Levels for Timing Specifications
= 2MHz.
0.2*OV
DD
A
DD
= 25°C. (Note 4)
CONDITIONS
(Note 11)
(Note 11)
t
C
C
C
(Note 11)
(Note 11)
SCKCH
L
L
L
without
= 20pF (Note 11)
= 20pF (Note 10)
= 20pF (Note 10)
0.8*OV
0.2*OV
= t
The
t
DELAY
SSDISCK
DD
DD
l
denotes the specifications which apply over the full operating
Note 7: Zero-scale error is the offset voltage measured from 0.5LSB
when the output code flickers between 0000 0000 0000 0000 and
0000 0000 0000 0001. Full-scale error is the deviation of the last code
transition from ideal and includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale 5V input with a
5V reference voltage.
Note 9: f
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OV
and OV
Note 12: t
100MHz for rising capture.
+ t
DSDO
DD
50%
(Note 11)
SMPL
SCK
= 5.25V.
of 10ns maximum allows a shift clock frequency up to
= 2MHz, I
t
WIDTH
REF
l
l
l
l
l
l
l
l
l
varies proportionately with sample rate.
50%
MIN
13.5
4
4
1
1
237016 F01
LTC2370-16
TYP
DD
= 1.71V, OV
MAX
9.5
16
13
5
DD
= 2.5V
237016fa
UNITS
5
ns
ns
ns
ns
ns
ns
ns
ns
ns