74LCX573M STMICROELECTRONICS [STMicroelectronics], 74LCX573M Datasheet

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74LCX573M

Manufacturer Part Number
74LCX573M
Description
OCTAL D-TYPE LATCH NON-INVERTING (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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DESCRIPTION
The 74LCX573 is a low voltage CMOS OCTAL
D-TYPE
NON-INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
These 8 bit D-Type latch are controlled by a latch
PIN CONNECTION AND IEC LOGIC SYMBOLS
September 2001
5V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED :
t
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
PD
PLH
OH
CC
= 8.0 ns (MAX.) at V
| = I
(OPR) = 2.0V to 3.6V (1.5V Data
t
PHL
LATCH
OL
= 24mA (MIN) at V
OCTAL D-TYPE LATCH NON-INVERTING (3-STATE)
with
WITH 5V TOLERANT INPUTS AND OUTPUTS
3
CC
= 3V
STATE
CC
= 3V
OUTPUT
2
MOS
ORDER CODES
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input. When the LE is
taken low, the Q outputs will be latched at the logic
level of D input data. While the (OE) input is low,
the 8 outputs will be in a normal logic state (high or
low logic level) and while (OE) is in high level, the
outputs will be in a high impedance state.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PACKAGE
TSSOP
SOP
SOP
74LCX573M
TUBE
74LCX573
TSSOP
74LCX573MTR
74LCX573TTR
T & R
1/10

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74LCX573M Summary of contents

Page 1

... It has same speed performance at 3.3V than 5V STATE OUTPUT AC/ACT family, combined with a lower power 2 consumption. MOS All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74LCX573 SOP TSSOP TUBE SOP 74LCX573M 74LCX573MTR 74LCX573TTR T & R 1/10 ...

Page 2

INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION State Output Enable Input (Active LOW Data Inputs 12, 13, 14, Q0 ...

Page 3

ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage Input Voltage Output Voltage (OFF State Output Voltage (High or Low State) (note Input Diode Current Output ...

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DC SPECIFICATIONS Symbol Parameter V High Level Input IH Voltage V Low Level Input IL Voltage V High Level Output OH Voltage V Low Level Output OL Voltage I Input Leakage I Current I Power Off Leakage off Current ...

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AC ELECTRICAL CHARACTERISTICS Symbol Parameter t t Propagation Delay PLH PHL Time ( Propagation Delay PLH PHL Time ( Output Enable Time PZL PZH to HIGH and LOW level t t Output ...

Page 6

TEST CIRCUIT PLH PHL PZL PLZ PZH PHZ equivalent (includes jig and probe capacitance 500 or equivalent ...

Page 7

WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 74LCX573 7/10 ...

Page 8

DIM. MIN 0 0. 12.60 E 10. 7. 8/10 SO-20 MECHANICAL DATA mm. TYP MAX. 2.65 0.2 2.45 0.49 0.32 0.5 45° (typ.) ...

Page 9

TSSOP20 MECHANICAL DATA DIM. MIN 0.05 A2 0.8 b 0.19 c 0.09 D 6.4 E 6.2 E1 4.3 e 0.65 BSC K 0° PIN 1 IDENTIFICATION 1 mm. TYP MAX. MIN. 1.2 ...

Page 10

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its ...

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