74LCX125TTR STMicroelectronics, 74LCX125TTR Datasheet

IC BUFFER TRI-ST QD LV 14TSSOP

74LCX125TTR

Manufacturer Part Number
74LCX125TTR
Description
IC BUFFER TRI-ST QD LV 14TSSOP
Manufacturer
STMicroelectronics
Series
74LCXr
Datasheet

Specifications of 74LCX125TTR

Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
1
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Logic Device Type
Buffer, Non Inverting
Supply Voltage Range
2V To 3.6V
Logic Case Style
TSSOP
No. Of Pins
14
Operating Temperature Range
-40°C To +85°C
Rohs Compliant
Yes
Logic Family
LCX
Number Of Channels Per Chip
4
Polarity
Non-Inverting
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
High Level Output Current
- 24 mA
Low Level Output Current
24 mA
Minimum Operating Temperature
- 40 C
Number Of Lines (input / Output)
4 / 3
Output Type
3-State
Propagation Delay Time
6 ns at 2.7 V, 5.2 ns at 3 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-6649-2
74LCX125TTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LCX125TTR
Manufacturer:
NXP
Quantity:
10
Part Number:
74LCX125TTR
Manufacturer:
ST
Quantity:
20 000
Part Number:
74LCX125TTR
Manufacturer:
STM
Quantity:
15 015
Company:
Part Number:
74LCX125TTR
Quantity:
1 100
Order codes
Features
July 2006
5V tolerant inputs and outputs
High speed:
– t
Power down protection on inputs and outputs
Symmetrical output impedance:
– |I
PCI bus levels guaranteed at 24mA
Balanced propagation delays:
– t
Operating voltage range:
– V
Pin and function compatible with
74 series 125
Latch-up performance exceeds
500mA (JESD 17)
ESD performance:
– HBM > 2000V
(MIL STD 883 method 3015); MM > 200V
PD
PLH
OH
CC
= 5.2ns (Max) at V
74LCX125MTR
| = I
74LCX125TTR
≅ t
(Opr) = 2.0V to 3.6V
Part number
PHL
OL
= 24mA (Min) at V
CC
= 3V
Low voltage CMOS quad bus buffer (3-State)
CC
= 3V
TSSOP14
Package
SO-14
Rev 6
with 5V tolerant inputs and outputs
Description
The 74LCX125 is a low voltage CMOS quad bus
buffer fabricated with sub-micron silicon gate and
double-layer metal wiring C
ideal for low power and high speed 3.3V
applications; it can be interfaced to 5V signal
environment for both inputs and outputs.
The device requires the 3-STATE control input G
to be set high to place the output in to the high
impedance state.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
SO-14
Tape and reel
Tape and reel
2
Packaging
MOS technology. It is
74LCX125
TSSOP14
www.st.com
1/16
16

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74LCX125TTR Summary of contents

Page 1

... ESD performance: – HBM > 2000V (MIL STD 883 method 3015); MM > 200V Order codes Part number 74LCX125MTR 74LCX125TTR July 2006 Low voltage CMOS quad bus buffer (3-State) with 5V tolerant inputs and outputs = Description The 74LCX125 is a low voltage CMOS quad bus ...

Page 2

Contents Contents 1 Logic symbols and I/O equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin settings . . . ...

Page 3

Logic symbols and I/O equivalent circuit Figure 1. IEC logic symbols Figure 2. Input and output equivalent circuit Logic symbols and I/O equivalent circuit 3/16 ...

Page 4

Pin settings 2 Pin settings 2.1 Pin connection Figure 3. Pin connection (top through view) 2.2 Pin description Table 1. Pin description Pin N° 10 2.3 Truth ...

Page 5

... STMicroelectronics sure program and other relevant quality documents. Table 3. Absolute maximum ratings ...

Page 6

Electrical characteristics 4 Electrical characteristics Table 5. DC specifications Symbol High level input V IH voltage Low level input V IL voltage High level output V OH voltage Low level output V OL voltage I Input leakage current 2.7 to ...

Page 7

Table 7. AC electrical characteristics Symbol Parameter t t Propagation delay PLH PHL time t t Output enable PZL PZH time to HIGH and LOW level t t Output disable PLZ PHZ time to HIGH and LOW level t ...

Page 8

Test circuit 5 Test circuit Figure 4. Test circuit Table 9. Test Circuit C = 50pF or equivalent (includes jig and probe capacitance) L Ω 500 or equivalent pulse generator (typically 50 T ...

Page 9

Waveforms Figure 5. Propagation delay (f = 1MHz; 50% duty cycle) Figure 6. Output enable and disable time (f = 1MHz; 50% duty cycle) Waveforms 9/16 ...

Page 10

Package mechanical data 7 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package ...

Page 11

DIM ddd SO-14 MECHANICAL DATA mm. MIN. TYP MAX. 1.35 1.75 0.1 0.25 1.10 1.65 0.33 0.51 0.19 0.25 8.55 8.75 3.8 4.0 1.27 5.8 6.2 0.25 ...

Page 12

Package mechanical data DIM PIN 1 IDENTIFICATION 12/16 TSSOP14 MECHANICAL DATA mm. MIN. TYP MAX. 1.2 0.05 0.15 0.8 1 1.05 0.19 0.30 0.09 0.20 4.9 5 ...

Page 13

DIM Tape & Reel SO-14 MECHANICAL DATA mm. MIN. TYP MAX. 330 12.8 13.2 20.2 60 22.4 6.4 6.6 9 9.2 2.1 2.3 3.9 4.1 7.9 8.1 Package mechanical ...

Page 14

Package mechanical data DIM 14/16 Tape & Reel TSSOP14 MECHANICAL DATA mm. MIN. TYP MAX. 330 12.8 13.2 20.2 60 22.4 6.7 6.9 5.3 5.5 1.6 1.8 3.9 4.1 7.9 ...

Page 15

Revision history Table 10. Revision history Date 15-Sep-2004 13-Jul-2006 Revision 5 Ordering codes revision - pag New template, temperature ranges updated Revision history Changes 15/16 ...

Page 16

... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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