AT28HC64B_08 ATMEL [ATMEL Corporation], AT28HC64B_08 Datasheet - Page 3

• Manufacturer Part Number: AT28HC64B_08
• Description: 64K (8K x 8) High Speed Parallel EEPROM with Page Write and Software Data Protection
• Manufacturer: ATMEL [ATMEL Corporation]

3. Block Diagram
4. Device Operation
4.1
4.2
4.3
4.4
0274K–PEEPR–8/08
Read
Byte Write
Page Write
DATA Polling
The AT28HC64B is accessed like a Static RAM. When CE and OE are low and WE is high,
the data stored at the memory location determined by the address pins is asserted on the out-
puts. The outputs are put in the high-impedance state when either CE or OE is high. This dual
line control gives designers flexibility in preventing bus contention in their systems.
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a
write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last.
The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it
will automatically time itself to completion. Once a programming operation has been initiated
and for the duration of t
The page write operation of the AT28HC64B allows 1 to 64 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; after the first byte is written, it can then be followed by 1 to 63
additional bytes. Each successive byte must be loaded within 150 µs (t
byte. If the t
the internal programming operation. All bytes during a page write operation must reside on the
same page as defined by the state of the A6 to A12 inputs. For each WE high-to-low transition
during the page write operation, A6 to A12 must be the same.
The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be
loaded in any order and may be altered within the same load period. Only bytes which are
specified for writing will be written; unnecessary cycling of other bytes within the page does
not occur.
The AT28HC64B features DATA Polling to indicate the end of a write cycle. During a byte or
page write cycle, an attempted read of the last byte written will result in the complement of the
written data to be presented on I/O7. Once the write cycle has been completed, true data is
valid on all outputs, and the next write cycle may begin. DATA Polling may begin at any time
during the write cycle.
BLC
limit is exceeded, the AT28HC64B will cease accepting data and commence
ADDRESS
INPUTS
GND
VCC
WE
OE
CE
WC
, a read operation will effectively be a polling operation.
OE, CE and WE
X DECODER
Y DECODER
LOGIC
DATA INPUTS/OUTPUTS
INPUT/OUTPUT
IDENTIFICATION
CELL MATRIX
DATA LATCH
I/O0 - I/O7
BUFFERS
Y-GATING
AT28HC64B
BLC
) of the previous
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