AT28HC64B_08 ATMEL [ATMEL Corporation], AT28HC64B_08 Datasheet - Page 4

• Manufacturer Part Number: AT28HC64B_08
• Description: 64K (8K x 8) High Speed Parallel EEPROM with Page Write and Software Data Protection
• Manufacturer: ATMEL [ATMEL Corporation]

4.5
4.6
4.6.1
4.6.2
4.7
4
Toggle Bit
Data Protection
Device Identification
AT28HC64B
Hardware Protection
Software Data Protection
In addition to DATA Polling, the AT28HC64B provides another method for determining the end
of a write cycle. During the write operation, successive attempts to read data from the device
will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop
toggling, and valid data will be read. Toggle bit reading may begin at any time during the write
cycle.
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel
the memory against inadvertent writes.
Hardware features protect against inadvertent writes to the AT28HC64B in the following ways:
(a) V
delay – once V
before allowing a write; (c) write inhibit – holding any one of OE low, CE high or WE high inhib-
its write cycles; and (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs
will not initiate a write cycle.
A software-controlled data protection feature has been implemented on the AT28HC64B.
When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP
feature may be enabled or disabled by the user; the AT28HC64B is shipped from Atmel with
SDP disabled.
SDP is enabled by the user issuing a series of three write commands in which three specific
bytes of data are written to three specific addresses (refer to the “Software Data Protection
Algorithm” diagram on
the entire AT28HC64B will be protected against inadvertent writes. It should be noted that
even after SDP is enabled, the user may still perform a byte or page write to the AT28HC64B.
This is done by preceding the data to be written by the same 3-byte command sequence used
to enable SDP.
Once set, SDP remains active unless the disable command sequence is issued. Power transi-
tions do not disable SDP, and SDP protects the AT28HC64B during power-up and power-
down conditions. All command sequences must conform to the page write timing specifica-
tions. The data in the enable and disable command sequences is not actually written into the
device; their addresses may still be written with user data in either a byte or page write
operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence
will start the internal write timers. No data will be written to the device, however. For the dura-
tion of t
An extra 64 bytes of EEPROM memory are available to the user for device identification. By
raising A9 to 12 V ±0.5 V and using address locations 1FC0H to 1FFFH, the additional bytes
may be written to or read from in the same manner as the regular memory array.
CC
WC
sense – if V
, read operations will effectively be polling operations.
CC
has reached 3.8 V, the device will automatically time out 5 ms (typical)
CC
®
has incorporated both hardware and software features that will protect
is below 3.8 V (typical), the write function is inhibited; (b) V
page
10). After writing the 3-byte command sequence and waiting t
0274K–PEEPR–8/08
CC
power-on
WC
,