W25X10BLSNIG WINBOND [Winbond], W25X10BLSNIG Datasheet
W25X10BLSNIG
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W25X10BLSNIG Summary of contents
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... AND 4M-BIT 2.5V SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL I/O SPI W25X10BL/20BL/40BL Publication Release Date: October 14, 2009 - 1- Preliminary -- Revision A ...
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... BUSY .............................................................................................................................. 11 9.1.2 Write Enable Latch (WEL) ............................................................................................. 11 9.1.3 Block Protect Bits (BP2, BP1, BP0) ............................................................................... 11 9.1.4 Top/Bottom Block Protect (TB) ....................................................................................... 11 9.1.5 Reserved Bits ................................................................................................................. 11 9.1.6 Status Register Protect (SRP) ........................................................................................ 12 9.1.7 Status Register Memory Protection ................................................................................ 13 9.2 INSTRUCTIONS ........................................................................................................... 14 9.2.1 Manufacturer and Device Identification .......................................................................... 14 9.2.2 Instruction Set ................................................................................................................ 15 9.2.3 Write Enable (06h) ......................................................................................................... 16 9.2.4 Write Disable (04h) ........................................................................................................ 16 9.2.5 Read Status Register (05h) ............................................................................................ 18 9 ...
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Fast Read Dual Output (3Bh) ......................................................................................... 23 9.2.10 Fast Read Dual I/O (BBh) ............................................................................................ 24 9.2.11 Continuous Read Mode Bits (M7-0) ............................................................................. 26 9.2.12 Continuous Read Mode Reset (FFFFh) ....................................................................... 26 9.2.13 Page Program (02h) ..................................................................................................... 27 9.2.14 Sector ...
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... Auto-increment Read capability • Efficient “Continuous Read Mode” – Low Instruction overhead – Continuous Read – As few as 8 clocks to address memory – Allows true XIP (execute in place) operation W25X10BL/20BL/40BL • Software and Hardware Write Protection – Write-Protect all or portion of memory – ...
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PIN CONFIGURATION SOIC 150-MIL / 208-MIL Figure 1a. W25X10BL/20BL/40BL Pin Assignments, 8-pin SOIC 150 / 208-mil (Package Code SN & SS) 4. PAD CONFIGURATION WSON 6X5-MM Figure 1b. W25X10BL/20BL/40BL Pad Assignments, 8-pad WSON 6X5-mm (Package Code ZP) W25X10BL/20BL/40BL Publication ...
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PIN CONFIGURATION PDIP 300-MIL Figure 1c. W25X40BL Pin Assignments, 8-pin PDIP (Package Code DA) 6. PIN DESCRIPTION SOIC 150 / 208-MIL, PDIP 300-MIL, WSON 6X5-MM PIN NO. PIN NAME 1 / (IO1) 3 /WP 4 GND 5 ...
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... The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (BP2, BP1, and BP0) bits and Status Register Protect (SRP) bit, a portion or the entire memory array can be hardware protected. The /WP pin is active low. ...
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BLOCK DIAGRAM Block Segmentation xxFF00h xxFFFFh • Sector 15 (4KB) • xxF000h xxF0FFh xxEF00h xxEFFFh • Sector 14 (4KB) • xxE000h xxE0FFh xxDF00h xxDFFFh • Sector 13 (4KB) • xxD000h xxD0FFh • • • xx2F00h xx2FFFh • Sector 2 ...
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FUNCTIONAL DESCRIPTION 8.1 SPI OPERATIONS 8.1.1 Standard SPI Instructions The W25X10BL/20BL/40BL are accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI ...
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... Status Register Protect (SRP) and Block Protect (TB, BP2, BP1, and BP0) bits. These Status Register bits allow a portion or all of the memory to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control ...
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... The Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The TB bit is non-volatile and the factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction provided that the Write Enable instruction has been issued ...
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Status Register Protect (SRP) The Status Register Protect (SRP) bit is a non-volatile read/write bit in status register (S7) that can be used in conjunction with the Write Protect (/WP) pin to disable writes to status register. When the ...
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... W25X20BL (2M-BIT) MEMORY PROTECTION BLOCK(S) ADDRESSES NONE NONE 3 030000h - 03FFFFh 2 and 3 020000h - 03FFFFh 0 000000h - 00FFFFh 0 and 1 000000h - 01FFFFh 0 thru 3 000000h - 03FFFFh W25X10BL (1M-BIT) MEMORY PROTECTION BLOCK(S) ADDRESSES NONE NONE 1 010000h - 01FFFFh 0 000000h - 00FFFFh 0 and 1 000000h - 01FFFFh Publication Release Date: October 14, 2009 - 13 - DENSITY PORTION ...
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... This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed ...
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... A15–A8 A7–A0 A23–A16 A15–A8 A7–A0 dummy dummy dummy dummy dummy 00h (MF[7:0], A23-A8 A7-A0, M[7:0] ID[7:0]) (M7-M0) (ID15-ID8) (ID7-ID0) Manufacturer Memory Type Capacity dummy dummy dummy Publication Release Date: October 14, 2009 - 15 - BYTE BYTE 6 N-BYTES 5 (2) (Next (D7–D0) continuous byte) (Next Byte) dummy (D7–D0) continuous ...
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... Write Enable for Volatile Status Register (50h) The non-volatile Status Register bits described in section 9.1 can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits ...
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Write Disable (04h) The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into ...
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Read Status Register (05h) The Read Status Register instruction allows the 8-bit Status Register to be read. The instruction is entered by driving /CS low and shifting the instruction code “05h” into the DIO pin on the rising edge ...
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Write Status Register (01h) The Write Status Register instruction allows the Status Register to be written. Only non-volatile Status Register bits SRP, TB, BP2, BP1, BP0 (bits 7 thru 2 of Status Register) can be written to. All other ...
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Figure 8. Write Status Register Instruction Sequence Diagram - 20 - W25X10BL/20BL/40BL ...
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... DIO pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data ...
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Fast Read (0Bh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of F eight “dummy” clocks after the 24-bit address as shown in figure 10. The ...
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Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins, DO and DIO, instead of just DO. This allows data ...
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Fast Read Dual I/O (BBh) The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO and similar to the Fast Read Dual Output (3Bh) instruction but with ...
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Figure 12b. Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10) W25X10BL/20BL/40BL Publication Release Date: October 14, 2009 - 25 - Preliminary -- Revision A ...
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... Continuous Read Mode Bits (M7-0) The “Continuous Read Mode” bits are used in conjunction with the “Fast Read Dual I/O” instruction to provide the highest random Flash memory access rate with minimum SPI instruction overhead, thus allow true XIP (execute in place performed on serial flash devices. ...
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... After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (BP2, BP1, and BP0) bits (see Status Register Memory Protection table). ...
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... Sector Erase (20h) The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Block Erase (52h) The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Block Erase (D8h) The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Chip Erase (C7h or 60h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ...
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Release Power-down / Device ID (ABh) The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state, obtain the devices electronic identification (ID) number or do ...
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Figure 21. Release Power-down / Device ID Instruction Sequence Diagram - 34 - W25X10BL/20BL/40BL ...
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Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down/ Device ID instruction that provides both JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/Device ID instruction ...
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Read Manufacturer / Device ID Dual I/O (92h) The Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at ...
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Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25X10BL/20BL/40BL device. The ID number can be used in conjunction with user software methods to help prevent ...
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... JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 25. For memory type and capacity values refer to Manufacturer and Device Identification table. ...
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ELECTRICAL CHARACTERISTICS 10.1 Absolute Maximum Ratings PARAMETERS Supply Voltage Voltage Applied to Any Pin Transient Voltage on any Pin Storage Temperature Lead Temperature Electrostatic Discharge Voltage Notes: 1. Specification for W25X10BL/20BL/40BL are preliminary. See preliminary designation at the end ...
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Power-up Timing and Write Inhibit Threshold PARAMETER VCC (min) to /CS Low Time Delay Before Write Instruction Write Inhibit Threshold Voltage Note: 1. These parameters are characterized only. W25X10BL/20BL/40BL SYMBOL t (1) VSL t (1) PUW V (1) WI ...
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DC Electrical Characteristics PARAMETER SYMBOL CONDITIONS Input Capacitance C (1) IN Output Capacitance Cout (1) Input Leakage I LI I/O Leakage I LO Standby Current Power-down Current Current Read Data / I CC ...
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AC Measurement Conditions PARAMETER Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. W25X10BL/20BL/40BL ...
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AC Electrical Characteristics DESCRIPTION Clock frequency for all instructions, except Read Data (03h) 2.3V-3.6V VCC & Industrial Temperature Clock freq. Read Data instruction 03h Clock High, Low Time, for Fast Read (0Bh, 3Bh) / other instructions except Read Data ...
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AC Electrical Characteristics ( DESCRIPTION /HOLD Active Setup Time relative to CLK /HOLD Active Hold Time relative to CLK /HOLD Not Active Setup Time relative to CLK /HOLD Not Active Hold Time relative to CLK /HOLD to Output Low-Z ...
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Serial Output Timing 10.9 Input Timing 10.10 Hold Timing W25X10BL/20BL/40BL Publication Release Date: October 14, 2009 - 45 - Preliminary -- Revision A ...
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PACKAGE SPECIFICATION 11.1 8-Pin SOIC 150-mil (Package Code SN) 1 SYMBOL (3) E ( θ Notes: 1. Controlling dimensions: millimeters, unless otherwise specified. 2. BSC = Basic ...
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SOIC 208-mil (Package Code SS) SYMBOL MIN A 1.75 A1 0.05 A2 1.70 b 0.35 C 0.19 D 5.18 D1 5.13 E 5. 7. θ 0° Notes: 1. Controlling dimensions: ...
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PDIP 300-mil (Package Code DA) Symbol Min A --- A1 0.25 A2 3.18 B 0.41 B1 1. 7.37 E1 6.22 e1 2.29 L 3.05 α 8. --- W25X10BL/20BL/40BL Millimeters ...
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WSON (Package Code ZP) SYMBOL MIN A 0.70 A1 0. 5.90 D2 3.35 4. (2) L 0.55 y 0.00 W25X10BL/20BL/40BL MILLIMETERS TYP. MAX MIN 0.75 0.80 0.0275 0.02 ...
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WSON 6x5mm Cont’d. SYMBOL SOLDER PATTERN Notes: 1. Advanced Packaging Information; please contact Winbond for the latest minimum and maximum specifications. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E ...
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... ORDERING INFORMATION W = Winbond 25X = spiFlash Serial Flash Memory with 4KB sectors, Dual Outputs 40 = 4M-bit 20 = 2M-bit 10 = 1M-bit L = 2. 8-pin SOIC 150-mil pin SOIC 208-mil I = Industrial (-40°C to +85° Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb Notes: 1a. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T) or Tray (shape S), when placing orders. 1b. The “ ...
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... ZP 2M-bit WSON-8 6x5mm 4M-bit DA 4M-bit PDIP-8 300mil Notes: 1. For WSON packages, the package type ZP is not used in the top side marking. W25X10BL/20BL/40BL PRODUCT NUMBER W25X10BLSNIG W25X20BLSNIG W25X40BLSNIG W25X40BLSSIG W25X10BLZPIG W25X20BLZPIG W25X40BLZPIG W25X40BLDAIG - 52 - TOP SIDE MARKING 25X10BLNIG 25X20BLNIG 25X40BLNIG 25X40BLSIG ...
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REVISION HISTORY VERSION DATE PAGE A 10/14/09 Preliminary Designation The “Preliminary” designation on a Winbond datasheet indicates that the product is not fully characterized. The specifications are subject to change and are not g authorized sales representative should be ...