HYB3165165TL-50 SIEMENS [Siemens Semiconductor Group], HYB3165165TL-50 Datasheet

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HYB3165165TL-50

Manufacturer Part Number
HYB3165165TL-50
Description
4M x 16-Bit Dynamic RAM
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
Semiconductor Group
4M x 16-Bit Dynamic RAM
(4k & 8k Refresh, EDO-version)
Preliminary Information
4 194 304 words by 16-bit organization
0 to 70 ˚C operating temperature
Fast access and cycle time
RAS access time:
50 ns (-50 version)
60 ns (-60 version)
Cycle time:
84 ns (-50 version)
104 ns (-60 version)
CAS access time:
13 ns ( -50 version)
15 ns ( -60 version)
Hyper page mode (EDO) cycle time
20 ns (-50 version)
25 ns (-60 version)
Single + 3.3 V ( 0.3V) power supply
Low power dissipation
max. 396 active mW ( HYB 3164165T(L)-50)
max. 360 active mW ( HYB 3164165T(L)-60)
max. 504 active mW ( HYB 3165165T(L)-50)
max. 432 active mW ( HYB 3165165T(L)-60)
7.2 mW standby (TTL)
720 W standby (MOS)
14.4 mW Self Refresh (L-version only)
Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh and self refresh modes
Hyper page mode (EDO) capability
2 CAS / 1 WE byte control
8192 refresh cycles/128 ms , 13 R/ 9C addresses (HYB 3164165T(L))
4096 refresh cycles/ 64 ms , 12 R/ 10C addresses (HYB 3165165T(L))
Plastic Package:
P-TSOPII-54-1 500 mil
31
HYB 3164(5)165T(L)
HYB 3164165T(L) -50/-60
HYB 3165165T(L) -50/-60

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HYB3165165TL-50 Summary of contents

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Dynamic RAM (4k & 8k Refresh, EDO-version) Preliminary Information 4 194 304 words by 16-bit organization • ˚C operating temperature • Fast access and cycle time • RAS access time (-50 version) ...

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This HYB3164(5)165 MBit dynamic RAM organized 4 194 304 x 16 bits. The device is fabricated in SIEMENS/IBM most advanced first generation 64Mbit CMOS silicon gate process technology. The circuit and process design allow this device to ...

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Pin 35 is A12 for HYB 3164165T(L) and N.C. for HYB 3165165T(L) Pin Configuration Semiconductor Group HYB3164(5)165T(L)-50/-60 P-TSOPII-54-1 (500 mil EDO-DRAM ...

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TRUTH TABLE FUNCTION RAS LCAS UCA Standby H L Read:Word Read:Lower Byte L L Read:Upper Byte Write:Word L (Early-Write) Write:Lower Byte L (Early-Write) Write:Upper Byte L (Early Write) Read-Modify- L Write Hyper Page Mode 1st L Read (Word) Cycle Hyper ...

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Block Diagram for HYB 3164165T(L) Semiconductor Group HYB3164(5)165T(L)-50/- EDO-DRAM 35 ...

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Block Diagram for HYB 3165165T(L) Semiconductor Group HYB3164(5)165T(L)-50/- EDO-DRAM 36 ...

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Absolute Maximum Ratings Operating temperature range.............................................................................................. ˚C Storage temperature range.........................................................................................– 150 ˚C Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V Power supply voltage....................................................................................................-0.5V to 4.6 V Power dissipation......................................................................................................................1.0 W Data out current (short circuit)..................................................................................................50 mA Note Stresses above ...

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DC Characteristics (cont’ ˚ Parameter Average Vcc supply current, during RAS-only refresh cycles: (RAS cycling: CAS = VIH: tRC = tRC min.) Average Vcc supply current, Hyper page ...

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AC Characteristics ˚ Parameter common parameters Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold ...

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AC Characteristics (cont’ ˚ Parameter Output buffer turn-off delay Output buffer turn-off delay from OE Data to CAS low delay Data to OE low delay CAS high to data ...

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AC Characteristics (cont’ ˚ Parameter OE pulse width OE hold time from CAS high WE pulse width to output disable at CAS high Output buffer turn-off delay from WE ...

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Notes: 1) All voltages are referenced to VSS. Vih may overshoot 0.2V for pulse widths of < 4ns with 3.3V. Vil may undershoot to -2.0V for pulse width < 4.0 ns with 3.3V. Pulse width measured at ...

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V IH RAS UCAS IH LCAS ASR V IH Row Address I/O (Inputs I/O (Outputs) V ...

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V IH RAS V IL UCAS V IH LCAS ASR V IH Row Address I/O (Inputs I/O (Outputs) V ...

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V IH RAS V IL UCAS V IH LCAS ASR V IH Row Address I/O (Inputs I/O (Outputs) V ...

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V IH RAS UCAS IH LCAS ASR V IH Address Row I/O (Inputs I/O (Outputs) V ...

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V IH RAS CRP V UCAS IH LCAS RAH t ASR V IH Address Row RAD I/O IH (Output) V ...

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V IH RAS CRP V UCAS IH LCAS RAH t ASR V IH Address Row RAD I/O IH (Output) V ...

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V IH RAS CRP V IH UCAS V IL LCAS t RAH t ASR V IH Address Row RAD I/O IH (Output) V ...

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V IH RAS CRP V IH UCAS V IL LCAS t RAH t ASR V IH Row Address Addr RAD t WCS ...

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V IH RAS CRP V IH UCAS V IL LCAS t RAH t ASR V IH Address Row RAD I/O IH (Input) V ...

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Hyper Page Mode (EDO) Read-Modify-Write Cycle Semiconductor Group HYB3164(5)165T(L)-50/- EDO-DRAM 52 WL17 ...

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V IH RAS UCAS IH LCAS ASR V IH Address I/O (Outputs “H” or “L” RAS Only Refresh Cycle Semiconductor Group t t RAS t RAH Row HI-Z ...

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V IH RAS RPC UCAS V IL LCAS OEZ CDD V IH I/O (Inputs ODD V OH I/O ...

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V IH RAS UCAS LCAS RAD t RAH t ASR V IH Address Row I/O (Inputs ...

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V IH RAS UCAS V IL LCAS t RAH t ASR V IH Address Row I/O (Input I/O (Output “H” or ...

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V IH RAS RPC UCAS V IL LCAS CDD V IH I/O (Inputs ODD t OEZ V OH I/O ...

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Read Cycle: RAS UCAS LCAS Address I/O (Inputs I/O (Outputs ...

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Package Outlines P-TSOPII-54-1 (500 mil) (Plastic Thin Small Outline Package Type II Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group HYB3164(5)165T(L)-50/- ...

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VAKAT ((60)) ...

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