TC55V16256JI TOSHIBA [Toshiba Semiconductor], TC55V16256JI Datasheet

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TC55V16256JI

Manufacturer Part Number
TC55V16256JI
Description
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
Manufacturer
TOSHIBA [Toshiba Semiconductor]
Datasheet
262,144-WORD BY 16-BIT CMOS STATIC RAM
DESCRIPTION
words by 16 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it
operates from a single 3.3 V power supply. Chip enable ( CE ) can be used to place the device in a low-power mode,
and output enable ( OE ) provides fast memory access. Data byte control signals ( LB , UB ) provide lower and upper
byte access. This device is well suited to cache memory applications where high-speed access and high-speed
storage are required. All inputs and outputs are directly LVTTL compatible. The TC55V16256JI/FTI is available in
plastic 44-pin SOJ and 44-pin TSOP with 400mil width for high density surface assembly. The TC55V16256JI/FTI
guarantees −40° to 85°C operating temperature so it is suitable for use in wide operating temperature system.
FEATURES
PIN ASSIGNMENT
GND
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
A15
A14
A13
A12
A16
WE
V
The TC55V16256JI/FTI is a 4,194,304-bit high-speed static random access memory (SRAM) organized as 262,144
CE
A4
A3
A2
A1
A0
DD
Fast access time (the following are maximum values)
Low-power dissipation
(the following are maximum values)
44 PIN SOJ
Operation (max)
(TC55V16256JI)
TC55V16256JI/FTI-12:12 ns
TC55V16256JI/FTI-15:15 ns
Standby:10 mA (both devices)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Cycle Time
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
230
UB
LB
12
A5
A6
A7
OE
I/O16
I/O15
I/O14
I/O13
GND
V
I/O12
I/O11
I/O10
I/O9
NU
A8
A9
A10
A11
A17
DD
(TOP VIEW)
200
15
GND
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
A15
A14
A13
A12
A16
WE
V
CE
44 PIN TSOP
A4
A3
A2
A1
A0
DD
170
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
150
(TC55V16256FTI)
25
mA
ns
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
UB
LB
A5
A6
A7
OE
I/O16
I/O15
I/O14
I/O13
GND
V
I/O12
I/O11
I/O10
I/O9
NU
A8
A9
A10
A11
A17
DD
Single power supply voltage of 3.3 V ± 0.3 V
Fully static operation
All inputs and outputs are LVTTL compatible
Output buffer control using OE
Data byte control using LB (I/O1 to I/O8) and
Package:
UB (I/O9 to I/O16)
SOJ44-P-400-1.27 (JI)
TSOP II44-P-400-0.80 (FTI)
PIN NAMES
I/O1 to I/O16 Data Inputs/Outputs
A0 to A17
LB , UB
GND
V
WE
CE
OE
NU
TC55V16256JI/FTI-12,-15
DD
Address Inputs
Chip Enable Input
Write Enable Input
Output Enable Input
Data Byte Control Inputs
Power (+3.3 V)
Ground
Not Usable (Input)
2002-01-07 1/11
(Weight: 1.64 g typ)
(Weight: 0.45 g typ)

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TC55V16256JI Summary of contents

Page 1

... All inputs and outputs are directly LVTTL compatible. The TC55V16256JI/FTI is available in plastic 44-pin SOJ and 44-pin TSOP with 400mil width for high density surface assembly. The TC55V16256JI/FTI guarantees −40° to 85°C operating temperature suitable for use in wide operating temperature system. ...

Page 2

... MEMORY CELL ARRAY 1,024 × 256 × 16 (4,194,304) CE SENSE AMP COLUMN DECODER COLUMN ADDRESS BUFFER CLOCK A10 A11 A12 CE RATING min (4 ns max) RC min (4 ns max) RC TC55V16256JI/FTI-12,- GND CE A16 VALUE UNIT −0.5 to 4.6 V −0.5* to 4.6 V −0. 0.5 ...

Page 3

... IL OUT Other Input = Other Input = − 0.2 V, Other Input = TEST CONDITION = GND GND V I/O TC55V16256JI/FTI-12,-15 MIN TYP MAX 3.0 3.3 3.6  + 0.3** 2 −0.3*  0.8 MIN TYP MAX −1  , −1  −1  −1  ...

Page 4

... High Impedance L H Output L L Input * High Impedance L H Input High Impedance * * H H High Impedance * * * * TC55V16256JI/FTI-12,-15 I/O9 to I/O16 POWER Output I DDO Output I DDO High Impedance I DDO Input I DDO Input I DDO High Impedance I DDO High Impedance I DDO High Impedance I DDS 2002-01-07 4/11 ...

Page 5

... TC55V16256JI/FTI -12 -15 MAX MIN MAX   15   9   12   12   12   0   0   8  ...

Page 6

... COE INDETERMINATE (See Note (See Note 6) t ODW (See Note 3) INDETERMINATE TC55V16256JI/FTI-12,- (See Note 6) t COD (See Note 6) t ODO (See Note VALID DATA OUT INDETERMINATE t WR (See Note 6) t OEW Hi-Z (See Note 4) ...

Page 7

... CONTROLLED) Address Hi-Z OUT WRITE CYCLE CONTROLLED) Address Hi-Z OUT D IN TC55V16256JI/FTI-12,-15 (See Note (See Note 6) (See Note ODW t COE (See Note 6) INDETERMINATE t DS VALID DATA IN (See Note 5) t ...

Page 8

... Output Enable Time ・・・・・・・・・・・・ OEW Output Disable Time ・・・・・・・・・・・・ ODW (A) 0.2 V VALID DATA OUT 0.2 V INDETERMINATE TC55V16256JI/FTI-12,-15 (B) 0.2 V Hi-Z 0.2 V INDETERMINATE 2002-01-07 8/11 ...

Page 9

... PACKAGE DIMENSIONS SOJ44-P-400-1.27 Weight: 1.64 g (typ) TC55V16256JI/FTI-12,-15 2002-01-07 9/11 ...

Page 10

... PACKAGE DIMENSIONS Weight: 0.45 g (typ) TC55V16256JI/FTI-12,-15 2002-01-07 10/11 ...

Page 11

... TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. TC55V16256JI/FTI-12,-15 000707EBA 2002-01-07 11/11 ...

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