AT45DB321C-RI ATMEL [ATMEL Corporation], AT45DB321C-RI Datasheet
AT45DB321C-RI
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AT45DB321C-RI Summary of contents
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... Green (Pb/Halide-free) Packaging Options Description The AT45DB321C is an SPI compatible, serial-interface Flash memory ideally suited storage applications. The AT45DB321C supports a 4-wire serial interface known as RapidS for applications requiring very high speed operations ...
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... To allow for simple in-system reprogrammability, the AT45DB321C does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB321C is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK) ...
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... The opcode is followed by three address bytes (which comprises 24-bit page and byte address sequence) and 32 don’t care clock cycles. The first bit of the 24-bit address sequence is reserved for upward and downward compatibility to larger and AT45DB321C [Preliminary] PAGE ARCHITECTURE 8 Pages ...
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... AT45DB321C [Preliminary] 4 smaller density devices (see the notes under “Command Sequence for Read/Write Operations (except Status Register Read)” on page 22. The next 13 bits (PA12-PA0) of the 24-bit address sequence specify which page of the main memory array to read, and the last 10 bits (BA9-BA0) of the 24-bit address sequence specify the starting byte address within the page. The 32 don’ ...
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... CS pin, the part will erase the selected block of eight pages. The erase operation is internally self-timed and should take place in a maximum time of t this time, the status register and the RDY/BUSY pin will indicate that the part is busy. AT45DB321C [Preliminary ...
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... Additional Commands AT45DB321C [Preliminary] 6 PA8 PA7 PA6 PA5 • • • • • • ...
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... The device density is indicated using bits and 2 of the status register. For the AT45DB321C, the four bits are 1, The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices ...
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... Sector Protection AT45DB321C [Preliminary] 8 Two protection methods, hardware and software controlled, are provided. The selection of which sectors to be protected/unprotected from program and erase operations is defined in the Sector Protection Register. SOFTWARE SECTOR PROTECTION: Sectors specified for protection in the Sector Protection Register can be protected from program and erase operations by issuing the Enable Sector Protection command ...
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... Register, the CS pin must first be asserted. Once the CS pin has been asserted, a 4-byte command sequence 32H, 00H, 00H, 00H and 32 don’t care clock cycles must be clocked in via the SI (serial input) pin. The 32 don’t care clock cycles are required to ini- AT45DB321C [Preliminary ...
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... AT45DB321C [Preliminary] 10 tialize the read operation. After the 32 don’t care clock cycles, any additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin. The read will begin with Byte_1 of the Sector Protection Register for Sector_0, followed with Byte_2 for Sector_1 ...
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... Bit 1 Bit 27H 00H 1FH Device ID Device ID Byte n Byte 1 Byte 2 AT45DB321C [Preliminary] Manufacturer ID 1FH = Atmel Family Code 001 = DataFlash Density Code 00111 = 32-Mbit MLC Code 000 = 1-bit/Cell Technology Product Version 00000 = Initial Version Byte Count 00H = 0 Bytes of Information 00H ...
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... Summary AT45DB321C [Preliminary] 12 The AT45DB321C contains a specialized register that can be used for security pur- poses in system design. The Security Register is a unique 128-byte register that is divided into two portions. The first 64 bytes (byte 0 to byte 63) of this page are allocated as a one-time user programmable space. Once these 64 bytes have been programmed, they should not be reprogrammed ...
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... Protection Register to change which sectors will be protected by the WP pin. The table below details the sector protection status for various scenarios of the WP pin, the Enable Sector Protection command, and the Disable Sector Protection command. 2 AT45DB321C [Preliminary] ) would enable the sector protection. WPE 3 ...
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... Command Issued High 2 Low High Command Issued during Period High High Issue Command AT45DB321C [Preliminary] 14 Disable Sector Protection Command – Command Issued x Not Issued Yet – Command Issued RESET: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state ...
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... If the memory cells were not erased or programmed, the algorithm loops back and erases or programs the memory cells again. The process will continue until the device is erased or programmed successfully. The erase and programming operations are internally self-timed and fixed timing is not recommended. AT45DB321C [Preliminary the mini ...
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... Page Rewrite” on page 6. 2. The Security Register Program command utilizes data stored in Buffer 1. Therefore, this command must be used in conjunc- tion with the Buffer 1 write command. See the Security Register description on page 12 for details. AT45DB321C [Preliminary] 16 SCK Mode RapidS Mode ...
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... N/A N AT45DB321C [Preliminary] Address Byte ...
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... Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH Notes during a buffer read maximum. CC1 AT45DB321C [Preliminary] 18 *NOTICE: + 0.6V CC Com. Ind the minimum specified datasheet value, the system should wait 20 ms before an opera- CC Condition CS, RESET all ...
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... WP Low to Protection Enabled WPE t WP High to Protection Disabled WPD Note: 1. Maximum specified frequency for SPI compatibility is 33 MHz. 2. Value are based on device characterization, not 100% tested in production. 3387B–DFLSH–9/04 AT45DB321C [Preliminary] Min Typ Max 250 250 250 ...
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... Input Test Waveforms and Measurement Levels DRIVING LEVELS Output Test Load AC Waveforms AT45DB321C [Preliminary] 20 3. < (10 DEVICE UNDER TEST Four different timing waveforms are shown below. Waveform 1 shows the SCK signal being low when CS makes a high-to-low transition, and waveform 2 shows the SCK sig- nal being high when CS makes a high-to-low transition ...
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... CSS VALID OUT VALID CSS VALID OUT VALID IN AT45DB321C [Preliminary CSH t DIS HIGH IMPEDANCE CSH t DIS HIGH IMPEDANCE CSH t HO DIS HIGH IMPEDANCE CSH t DIS HIGH IMPEDANCE ...
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... It is recommended that “r” logical “0” for densities of 32M bits or smaller. 3. For densities larger than 32M bits, the “r” bit becomes the most significant Page Address bit for the appropriate density. AT45DB321C [Preliminary bits ...
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... PA12-6 PA5-0, BFA9-8 BFA7 X···X, BFA9-8 BFA7-0 Starts self-timed erase/program operation CMD r , PA12-6 PA5-0, XX AT45DB321C [Preliminary] BUFFER 2 TO MAIN MEMORY PAGE PROGRAM BUFFER 2 (528 BYTES) BUFFER 2 WRITE · Completes writing into selected buffer · Starts self-timed erase/program operation n n+1 Last Byte · ...
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... Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer Buffer Read CS SI CMD SO Each transition represents 8 bits and 8 clock cycles AT45DB321C [Preliminary] 24 The following block diagram and waveforms illustrate the various read sequences available. FLASH MEMORY ARRAY MAIN MEMORY PAGE READ I/O INTERFACE SO PA5-0, BA9-8 BA7-0 ...
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... DATA OUT HIGH IMPEDANCE HIGH IMPEDANCE AT45DB321C [Preliminary] LSB MSB BIT 4223 BIT PAGE n PAGE n DATA OUT ...
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... CS SCK COMMAND OPCODE HIGH IMPEDANCE SO Manufacturer and Device ID Read (Opcode: 9FH) CS SCK COMMAND OPCODE HIGH IMPEDANCE SO AT45DB321C [Preliminary MSB ...
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... DATA OUT HIGH IMPEDANCE HIGH IMPEDANCE AT45DB321C [Preliminary] LSB MSB BIT 4223 BIT PAGE n PAGE n DATA OUT ...
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... CS SCK COMMAND OPCODE HIGH IMPEDANCE SO Manufacturer and Device ID Read (Opcode: 9FH) CS SCK COMMAND OPCODE HIGH IMPEDANCE SO AT45DB321C [Preliminary MSB ...
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... The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. 3387B–DFLSH–9/04 START provide address (82H, 85H) END AT45DB321C [Preliminary] and data BUFFER WRITE (84H, 87H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) ...
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... Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details. AT45DB321C [Preliminary] 30 START ...
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... AT45DB321C [Preliminary] PA5 PA4 PA3 PA2 - PA0 • • • • • • • ...
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... Wide, Plastic Gull Wing Small Outline Package (SOIC) AT45DB321C [Preliminary] 32 Ordering Code AT45DB321C-CC AT45DB321C-CNC AT45DB321C-TC AT45DB321C-CI AT45DB321C-TI Ordering Code AT45DB321C-CNU AT45DB321C-TU (1) Ordering Code AT45DB321C-RC AT45DB321C-RI Package Type Package Operation Range 24C1 Commercial 8CN3 ( 28T 24C1 Industrial 28T (- Package Operation Range ...
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... San Jose, CA 95131 R 3387B–DFLSH–9/ Ball Corner e 2.00 REF Ø TITLE 24C3, 24-ball ( Array), 1.0 mm Pitch 1.20 mm, Chip-scale Ball Grid Array Package (CBGA) AT45DB321C [Preliminary Side View COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL E 5.90 6.00 6.10 E1 4.0 TYP D 7.90 8 ...
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... All dimensions and tolerance conform to ASME Y 14.5M, 1994. 2. The surface finish of the package shall be EDM Charmille #24-27. 3. Unless otherwise specified tolerance: Decimal ±0.05, Angular ±2 4. Metal Pad Dimensions. 2325 Orchard Parkway San Jose, CA 95131 R AT45DB321C [Preliminary Top View Side View Pin1 Pad Corner L1 ...
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... Orchard Parkway San Jose, CA 95131 R 3387B–DFLSH–9/04 PIN SEATING PLANE A1 TITLE 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) AT45DB321C [Preliminary] 0º ~ 5º GAGE PLANE COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A – ...
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... PIN 0º ~ 8º Note: 1. Dimensions D and E1 do not include mold Flash or protrusion. Mold Flash or protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT45DB321C [Preliminary TITLE 28R, 28-lead, 0.330" Body Width, Plastic Gull Wing Small Outline (SOIC) ...
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... Everywhere You Are and RapidS are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trade- marks of others. Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 Microcontrollers 2325 Orchard Parkway ...