AT45DB321C-RI ATMEL [ATMEL Corporation], AT45DB321C-RI Datasheet - Page 12

• Manufacturer Part Number: AT45DB321C-RI
• Description: 32 MEGABIT 2.7 VOLT DATAFLASH
• Manufacturer: ATMEL [ATMEL Corporation]

Security Register
Operation Mode
Summary
12
AT45DB321C [Preliminary]
The AT45DB321C contains a specialized register that can be used for security pur-
poses in system design. The Security Register is a unique 128-byte register that is
divided into two portions. The first 64 bytes (byte 0 to byte 63) of this page are allocated
as a one-time user programmable space. Once these 64 bytes have been programmed,
they should not be reprogrammed. The remaining 64 bytes of this page (byte 64 to byte
127) are factory programmed by Atmel and will contain a unique number for each
device. The factory programmed data is fixed and cannot be changed.
The Security Register can be read by clocking in opcode 77H to the device followed by
three address bytes (which are comprised of 14 don’t care bits plus 10 address bits) and
32 don’t care clock cycles. See the opcode table on page 17.
To program the first 64 bytes of the Security Register, a two step sequence must be
used. The first step requires that the user loads the desired data into Buffer 1 by using
the Buffer 1 Write operation (opcode 84H – see Buffer Write description on page 5). The
user should specify the starting buffer address as location zero and should write a full
64 bytes of information into the buffer. Otherwise, the first 64 bytes of the buffer may
contain data that was previously stored in the buffer. It is not necessary to fill the remain-
ing 464 bytes (byte locations 64 through 127) of the buffer with data. After the Buffer 1
Write operation has been completed, the Security Register can be subsequently pro-
grammed by reselecting the device and clocking in opcode 9AH into the device followed
by three don’t care bytes (24 clock cycles). After the final don’t care clock cycle has
been completed, a low-to-high transition on the CS pin will cause the device to initiate
an internally self-timed program operation in which the contents of Buffer 1 will be pro-
grammed into the Security Register. Only the first 64 bytes of data in Buffer 1 will be
programmed into the Security Register; the remaining 464 bytes of the buffer will be
ignored. The Security Register program operation should take place in a maximum time
of t
The modes described can be separated into two groups – modes that make use of the
Flash memory array (Group A) and modes that do not make use of the Flash memory
array (Group B).
Group A modes consist of:
1. Main Memory Page Read
2. Continuous Array Read
3. Main Memory Page to Buffer 1 (or 2) Transfer
4. Buffer 1 (or 2) to Main Memory Page Program with Built-in Erase
5. Buffer 1 (or 2) to Main Memory Page Program without Built-in Erase
6. Main Memory Page Program through Buffer 1 (or 2)
7. Page Erase
8. Block Erase
9. Auto Page Rewrite
Group B modes consist of:
1. Buffer 1 (or 2) Read
2. Buffer 1 (or 2) Write
3. Status Register Read
4. Manufacturer and Device ID Read
If a Group A mode is in progress (not fully completed), then another mode in Group A
should not be started. However, during this time in which a Group A mode is in
P
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