TE28F200B5T80 INTEL [Intel Corporation], TE28F200B5T80 Datasheet
TE28F200B5T80
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TE28F200B5T80 Summary of contents
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... Based on Intel’s boot block architecture, the Smart 5 boot block memory family enables quick and easy upgrades for designs that demand state-of-the-art technology. This family of products comes in industry- standard packages: the 40-lead TSOP for very space-constrained 8-bit applications, 48-lead TSOP, ideal for board-constrained higher-performance 16-bit applications, and the rugged, easy to handle 44-lead PSOP ...
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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale ...
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... INTRODUCTION .............................................5 1.1 New Features in the Smart 5 Memory Products......................................................5 1.2 Product Overview.........................................5 2.0 PRODUCT DESCRIPTION..............................6 2.1 Pin Descriptions ...........................................6 2.2 Pinouts.........................................................8 2.3 Memory Blocking Organization...................10 2.3.1 One 16-KB Boot Block.........................10 2.3.2 Two 8-KB Parameter Blocks................10 2.3.3 Main Blocks - One 96-KB + Additional 128-KB Blocks....................................10 3.0 PRINCIPLES OF OPERATION .....................13 3.1 Bus Operations ..........................................13 3.1.1 Read....................................................13 3.1.2 Output Disable.....................................14 3.1.3 Standby ...............................................14 3.1.4 Word/Byte Configuration......................14 3.1.5 Deep Power-Down/Reset ....................14 3 ...
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... SMART 5 BOOT BLOCK MEMORY FAMILY REVISION HISTORY Number -001 Original Version -002 Minor changes throughout document. Section 3.1.5 and Figure 14 redone to clarify program/erase operation abort. Information added to Table 2, Figure 1, and Section 3.3 to clarify WP# on 8-Mbit, 44-PSOP. Read and Write Waveforms changed to numbered format. ...
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... Finally, Sections 6.0 and 7.0 provide ordering and reference information. 1.1 New Features in the Smart 5 Memory Products The Smart 5 boot block flash memory family offers identical features with the BV/CV/BE/CE SmartVoltage products, except the Smart 5 boot block -B5 parts only support read voltage ...
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... Consequently, the system Reset signal should be tied to RP# to reset the memory to normal read mode upon activation of the Reset signal. This also times at provides protection against unwanted command ...
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... INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption to standby levels. If CE# and RP# are high, but not at a CMOS high level, the standby current will increase due to current flow through the CE# and RP# input stages ...
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... DQ Not applicable to 28F004B5. V DEVICE POWER SUPPLY: 5 PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or PP programming data in each block, a voltage either applied to this pin. When V against Program and Erase commands. GND GROUND: For all internal circuitry. ...
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... Figure 2. 48-Lead TSOP Pinout Diagram ADVANCE INFORMATION SMART 5 BOOT BLOCK MEMORY FAMILY 28F400 44 RP# RP# 43 WE# WE PA28F200 Boot Block ...
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... The combination of block sizes in the boot block architecture allow the integration of several memories into a single chip. For the address locations of the blocks, see the memory maps in Figures and 7. 2.3.1 ONE 16-KB BOOT BLOCK The boot block is intended to replace a dedicated boot PROM in a microprocessor or microcontroller- based system ...
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... MAIN BLOCK 10000H 30000H 2FFFFH 0FFFFH 128-Kbyte MAIN BLOCK 00000H 20000H 1FFFFH 10000H 0FFFFH 00000H NOTE: Word addresses shown. Figure 4. Word-Wide x16-Mode Memory Maps (Top Boot) 3FFFFH 30000H 2FFFFH 20000H 1FFFFH 1FFFFH 128-Kbyte MAIN BLOCK 10000H 10000H 0FFFFH 0FFFFH 96-Kbyte MAIN BLOCK ...
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... BOOT BLOCK 00000H 00000H 28F200-B NOTE operation, the least significant system address should be connected to A Figure 7. Byte-Wide x8-Mode Memory Maps (Bottom Boot) 12 28F400-T FFFFFH 16-Kbyte BOOT BLOCK 16-Kbyte BOOT BLOCK FC000H FBFFFH 8-Kbyte PARAMETER BLOCK ...
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... The local CPU reads and writes flash memory in- 9 system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. Four control pins dictate the data flow in and out of the component: CE#, OE#, WE#, and RP#. These bus operations are summarized in Tables 3 and 4. ...
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... RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. 3.1.6 WRITE The CUI does not occupy an addressable memory location. Instead, commands are written into the CUI using standard microprocessor write timings PLPH when WE# and CE# are low, OE proper address and data (command) are presented ...
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... To program or erase the boot block, hold RP RP# must be at GND ± 0 meet the maximum deep power-down current specified. 10. This column does not apply to the E28F004B5 since x8-only device. ADVANCE INFORMATION SMART 5 BOOT BLOCK MEMORY FAMILY CE# OE# WE ...
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... SMART 5 BOOT BLOCK MEMORY FAMILY 3.2 Modes of Operation The flash memory has three read modes and two write modes. The read modes are read array, read identifier, and read status. The write modes are program and block erase. An additional mode, erase suspend to read, is available only during block erasures ...
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... Erase Suspend/Resume The Erase Suspend command (B0H) interrupts an erase operation in order to read data in another block of memory. While the erase is in progress, issuing the Erase Suspend command requests that the WSM suspend the erase algorithm after a certain latency period. After issuing the Erase Suspend command, write the Read Status Register command, then check bit SR ...
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... SMART 5 BOOT BLOCK MEMORY FAMILY To resume the erase operation, enable the chip by taking CE then issue the Erase Resume IL command, which continues the erase sequence to Table 5. Command Codes and Descriptions Code Device Mode 00 Invalid/ Unassigned commands that should not be used. Intel reserves the right to redefine Reserved these codes for future functions ...
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... PA = Address to be programmed Data to be programmed at location PA. 7. Either 40H or 10H commands is valid. 8. When writing commands to the device, the upper data bus [DQ draw. ADVANCE INFORMATION SMART 5 BOOT BLOCK MEMORY FAMILY Description = 0 for manufacturer, 0 First Bus Cycle Second Bus Cycle Oper Addr ...
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... SMART 5 BOOT BLOCK MEMORY FAMILY Table 7. Status Register Bit Definition WSMS ESS SR.7 WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE-SUSPEND STATUS (ESS Erase Suspended 0 = Erase In Progress/Completed SR.5 = ERASE STATUS (ES Error In Block Erasure 0 = Successful Block Erase SR.4 = PROGRAM STATUS (DWS Error in Byte/Word Program 0 = Successful Byte/Word Program SR ...
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... V Range Error Word/Byte Program SR.4 = Error 0 Word/Byte Program Successful Figure 8. Automated Word/Byte Program Flowchart ADVANCE INFORMATION SMART 5 BOOT BLOCK MEMORY FAMILY Bus Command Comments Operation Write Setup Data = 40H Program Addr = Word/Byte to Program Write Program Data = Data to Program Addr = Location to Program ...
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... SMART 5 BOOT BLOCK MEMORY FAMILY Start Write 20H, Block Address Write D0H and Block Address Read Status Register Suspend Erase Loop NO 0 YES Suspend SR.7 = Erase 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above ...
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... Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Read Array Data Erase Resumed Figure 10. Erase Suspend/Resume Flowchart ADVANCE INFORMATION SMART 5 BOOT BLOCK MEMORY FAMILY Bus Command Comments Operation Data = B0H Write Erase Suspend Addr = X Data = 70H Write ...
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... Power Reduction Control (PRC) circuitry allows the device to put itself into a low current state when not being accessed. After data is read from the memory array, PRC logic controls the device’s power consumption by entering the APS mode where typical I current is less than 1 mA ...
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... Using RP# properly during system reset is important with automated program/erase devices because the system expects to read from the flash memory when it comes out of reset CPU reset occurs without a flash memory reset, proper CPU initialization would not occur because the flash memory may in a mode other than Read Array. ...
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... SMART 5 BOOT BLOCK MEMORY FAMILY 5.0 ELECTRICAL SPECIFICATIONS 5.1 Absolute Maximum Ratings* Commercial Operating Temperature During Read/Erase/Program...... 0 °C to +70 °C Temperature Under Bias ....... –10 °C to +80 °C Extended Operating Temperature During Read/Erase/Program.. –40 °C to +85 °C Temperature Under Bias ....... –40 °C to +85 °C Storage Temperature................. – ...
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... CCES I V Standby Current 1 PP PPS I V Deep Power-Down 1 PP PPD Current I V Read Current 1 PP PPR ADVANCE INFORMATION SMART 5 BOOT BLOCK MEMORY FAMILY Typ Max Unit Comm Extended Test Condition ±1.0 ±1.0 µ Max ± 10 ± ...
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... SMART 5 BOOT BLOCK MEMORY FAMILY 5.4 DC Characteristics—Commercial and Extended Temperature Temp Sym Parameter Note Typ Max Typ Max Unit I V Program Current 1,4 PP PPW (Word or Byte Mode Erase Current 1,4 PP PPE I V Erase Susp Current 1 PP PPES I RP# Unlock Current 1,4 RP Identifier Current ...
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... V . Input rise and fall times (10% to 90%) <10 ns. TTL IH IL Figure 12. Standard Test Waveform ADVANCE INFORMATION SMART 5 BOOT BLOCK MEMORY FAMILY = 5 +25 °C. These currents are valid for all and not guaranteed in the range between PP PPLK to less than 1 mA typical, in static operation. ...
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... SMART 5 BOOT BLOCK MEMORY FAMILY DEVICE UNDER TEST NOTE: C includes jig capacitance. L Figure 13. Test Configuration Test Configuration Component Values Test Configuration C (pF Standard Test 100 580 5 V High-Speed Test 30 580 RP# ( PLPH ...
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... See Test Configuration (Figure 13 Standard Test component values. 6. Dynamic BYTE# switching between word and byte modes is not supported. Mode changes must be made when the device is in deep power-down or powered down. ADVANCE INFORMATION SMART 5 BOOT BLOCK MEMORY FAMILY Temp Commercial Speed ...
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... SMART 5 BOOT BLOCK MEMORY FAMILY Device and Address Selection V IH ADDRESSES (A) Address Stable CE# ( OE# ( WE# ( High Z DATA (D/ RP#( Figure 15. AC Waveforms for Read Operations 5.6 Erase and Program Timings—Commercial and Extended Temperature ± ...
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... Write pulse width high ( defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low WPH (whichever goes low first). Hence WPH WHWL ADVANCE INFORMATION SMART 5 BOOT BLOCK MEMORY FAMILY Comm Parameter Note Min Max Min Max Unit 450 ...
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... SMART 5 BOOT BLOCK MEMORY FAMILY ADDRESSES [ CE#(WE#) [E(W OE# [ WE#(CE#) [W(E High Z DATA [D/ 6. RP PPH V 1 PPH V [ PPLK V IL NOTE power-up and standby. ...
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... PSOP 48-Lead TSOP PA28F200B5T60 E28F200B5T60 PA28F200B5B60 E28F200B5B60 PA28F200B5T80 E28F200B5T80 PA28F200B5B80 E28F200B5B80 PA28F400B5T60 E28F400B5T60 PA28F400B5B60 E28F400B5B60 PA28F400B5T80 E28F400B5T80 PA28F400B5B80 E28F400B5B80 PA28F800B5T70 E28F800B5T70 PA28F800B5B70 E28F800B5B70 PA28F800B5T90 E28F800B5T90 PA28F800B5B90 E28F800B5B90 TB28F200B5T80 TE28F200B5T80 TB28F200B5B80 TE28F200B5B80 TB28F400B5T80 TE28F400B5T80 TB28F400B5B80 TE28F400B5B80 TB28F800B5T90 TE28F800B5T90 TB28F800B5B90 TE28F800B5B90 / 0599_16 35 ...
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... Low Power Boot Block Flash Memory Datasheet 28F002/400BX-T/B 4-Mbit Boot Block Flash Memory Datasheet 290451 297862 Smart 5 Boot Block Flash Memory Family 28F200B5, 28F400/004B5, 28F800B5 Specification Update NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’ ...
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... Program Status “1” Status Array Setup Read Read Program Identifier “1” ID Array Setup ADVANCE INFORMATION SMART 5 BOOT BLOCK MEMORY FAMILY APPENDIX A CHART Command Input (and Next State) Erase Erase Erase Erase Setup Confirm Susp. Resume (20H) (D0H) (B0H) (D0H) ...
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... SMART 5 BOOT BLOCK MEMORY FAMILY PRODUCT BLOCK DIAGRAM 38 APPENDIX B ADVANCE INFORMATION 7769_01 ...