DSPIC30F MICROCHIP [Microchip Technology], DSPIC30F Datasheet - Page 141

• Manufacturer Part Number: DSPIC30F
• Description: General Purpose and Sensor Families High-Performance Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

18.3.7
The DCI module has a dedicated 12-bit time base that
produces the bit clock. The bit clock rate (period) is set
by writing a non-zero 12-bit value to the BCG<11:0>
control bits in the DCICON1 SFR.
When the BCG<11:0> bits are set to zero, the bit clock
will be disabled. If the BCG<11:0> bits are set to a non-
zero value, the bit clock generator is enabled. These
bits should be set to ‘0’ and the CSCKD bit set to ‘1’ if
the serial clock for the DCI is received from an external
device.
The formula for the bit clock frequency is given in
Equation 18-2.
EQUATION 18-2:
The required bit clock frequency will be determined by
the system sampling rate and frame size. Typical bit
clock frequencies range from 16x to 512x the converter
sample rate depending on the data converter and the
communication protocol that is used.
To achieve bit clock frequencies associated with com-
mon audio sampling rates, the user will need to select
a crystal frequency that has an ‘even’ binary value.
Examples of such crystal frequencies are listed in
Table 18-1.
TABLE 18-1:
 2004 Microchip Technology Inc.
Note 1: When the CSCK signal is applied exter-
2.048 MHz
4.096 MHz
4.800 MHz
9.600 MHz
F
OSC
2: When the CSCK signal is applied exter-
BIT CLOCK GENERATOR
nally (CSCKD = 1), the BCG<11:0> bits
have no effect on the operation of the DCI
module.
nally (CSCKD = 1), the external clock
high and low times must meet the device
timing requirements.
F
BCK
DEVICE FREQUENCIES FOR
COMMON CODEC CSCK
FREQUENCIES
=
BIT CLOCK FREQUENCY
2 (BCG + 1)
PLL
16x
8x
8x
4x
•
F
CY
32.768 MIPs
32.768 MIPs
38.4 MIPs
38.4 MIPs
F
CYC
Preliminary
18.3.8
The sample clock edge (CSCKE) control bit determines
the sampling edge for the CSCK signal. If the CSCK bit
is cleared (default), data will be sampled on the falling
edge of the CSCK signal. The AC-Link protocols and
most Multi-Channel formats require that data be sam-
pled on the falling edge of the CSCK signal. If the
CSCK bit is set, data will be sampled on the rising edge
of CSCK. The I
sampled on the rising edge of the CSCK signal.
18.3.9
In most applications, the data transfer begins one
CSCK cycle after the COFS signal is sampled active.
This is the default configuration of the DCI module. An
alternate data alignment can be selected by setting the
DJST control bit in the DCICON2 SFR. When DJST = 1,
data transfers will begin during the same CSCK cycle
when the COFS signal is sampled active.
18.3.10
The TSCON SFR has control bits that are used to
enable up to 16 time slots for transmission. These con-
trol bits are the TSE<15:0> bits. The size of each time
slot is determined by the WS<3:0> word size selection
bits and can vary up to 16 bits.
If a transmit time slot is enabled via one of the TSE bits
(TSEx = 1), the contents of the current transmit shadow
buffer location will be loaded into the CSDO Shift regis-
ter and the DCI buffer control unit is incremented to
point to the next location.
During an unused transmit time slot, the CSDO pin will
drive ‘0’s or will be tri-stated during all disabled time
slots depending on the state of the CSDOM bit in the
DCICON1 SFR.
The data frame size in bits is determined by the chosen
data word size and the number of data word elements
in the frame. If the chosen frame size has less than 16
elements, the additional slot enable bits will have no
effect.
Each transmit data word is written to the 16-bit transmit
buffer as left justified data. If the selected word size is
less than 16 bits, then the LS bits of the transmit buffer
memory will have no effect on the transmitted data. The
user should write ‘0’s to the unused LS bits of each
transmit buffer location.
SAMPLE CLOCK EDGE
CONTROL BIT
DATA JUSTIFICATION
CONTROL BIT
TRANSMIT SLOT ENABLE BITS
2
S protocol requires that data be
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