ATMEGA325-16AJ ATMEL [ATMEL Corporation], ATMEGA325-16AJ Datasheet - Page 155

• Manufacturer Part Number: ATMEGA325-16AJ
• Description: 8-bit Microcontroller with In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either
Frame Formats
2570A–AVR–09/04
clock input (Slave) or clock output (Master). The dependency between the clock edges
and data sampling or data change is the same. The basic principle is that data input (on
RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is
changed.
Figure 71. Synchronous Mode XCK Timing.
The UCPOLn bit in UCSRnC selects which XCK clock edge is used for data sampling
and which is used for data change. As Figure 71 shows, when UCPOLn is zero the data
will be changed at rising XCK edge and sampled at falling XCK edge. If UCPOLn is set,
the data will be changed at falling XCK edge and sampled at rising XCK edge.
A serial frame is defined to be one character of data bits with synchronization bits (start
and stop bits), and optionally a parity bit for error checking. The USART accepts all 30
combinations of the following as valid frame formats:
•
•
•
•
A frame starts with the start bit followed by the least significant data bit. Then the next
data bits, up to a total of nine, are succeeding, ending with the most significant bit. If
enabled, the parity bit is inserted after the data bits, before the stop bits. When a com-
plete frame is transmitted, it can be directly followed by a new frame, or the
communication line can be set to an idle (high) state. Figure 72 illustrates the possible
combinations of the frame formats. Bits inside brackets are optional.
Figure 72. Frame Formats
St
(n)
P
UCPOL = 1
UCPOL = 0
1 start bit
5, 6, 7, 8, or 9 data bits
no, even or odd parity bit
1 or 2 stop bits
(IDLE)
Start bit, always low.
Data bits (0 to 8).
Parity bit. Can be odd or even.
RxD / TxD
RxD / TxD
St
XCK
XCK
0
1
2
3
ATmega325/3250/645/6450
4
FRAME
[5]
[6]
[7]
[8]
[P]
Sample
Sample
Sp1 [Sp2]
(St / IDLE)
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