P80C652EBB PHILIPS [NXP Semiconductors], P80C652EBB Datasheet - Page 8

• Manufacturer Part Number: P80C652EBB
• Description: CMOS single-chip 8-bit microcontrollers
• Manufacturer: PHILIPS [NXP Semiconductors]

Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.
1. These frequencies exceed the upper limit of 100kHz of the I
Phlips Semiconductors
ROM CODE PROTECTION
(83C652)
The 8XC652 has an additional security
feature. ROM code protection may be
selected by setting a mask–programmable
security bit (i.e., user dependent). This
feature may be requested during ROM code
submission. When selected, the ROM code is
protected and cannot be read out at any time
by any test mode or by any instruction in the
external program memory space.
The MOVC instructions are the only
instructions that have access to program
code in the internal or external program
memory. The EA input is latched during
RESET and is “don’t care” after RESET
(also if the security bit is not set). This
implementation prevents reading internal
program code by switching from external
program memory to internal program memory
during a MOVC instruction or any other
instruction that uses immediate data.
OSCILLATOR
CHARACTERISTICS
XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol,
page 2.
Table 2.
Serial Control Register (S1CON) – See Table 3
Table 3.
NOTES:
1997 Dec 05
S1CON (D8H)
CMOS single-chip 8-bit microcontrollers
Idle
Idle
Power-down
Power-down
CR2
0
0
0
0
1
1
1
1
MODE
CR1
External Pin Status During Idle and Power-Down Mode
Serial Clock Rates
CR2
0
0
1
1
0
0
1
1
ENS1 STA
CR0
0
1
0
1
0
1
0
1
PROGRAM
MEMORY
External
External
Internal
Internal
STO
0.24 < 62.5
0 to 255
BIT FREQUENCY (kHz) AT f
6MHz
31.25
SI
6.25
100
23
27
37
50
AA
To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.
Reset
A reset is accomplished by holding the RST
pin high for at least two machine cycles (24
oscillator periods), while the oscillator is
running. To insure a good power-on reset, the
RST pin must be high long enough to allow
the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At
power-on, the voltage on V
come up at the same time for a proper
start-up.
Idle Mode
In the idle mode, the CPU puts itself to sleep
while all of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers
remain intact during this mode. The idle
mode can be terminated either by any
CR1
0.49 < 62.5
ALE
0 to 254
12MHz
1
1
0
0
200
62.5
12.5
100
CR0
47
54
75
1
2
C-bus specification and cannot be used in an I
0.65 < 55.6
PSEN
0 to 253
16MHz
1
1
0
0
133
267
62.5
83.3
8
100
71
17
OSC
1
1
DD
and RST must
PORT 0
0.98 < 50.0
Float
Float
Data
Data
0 to 251
24MHz
107
125
150
200
400
94
25
1
1
1
1
1
enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
power-on reset.
Power-Down Mode
In the power-down mode, the oscillator is
stopped and the instruction to invoke
power-down is the last instruction executed.
Only the contents of the on-chip RAM are
preserved. A hardware reset is the only way
to terminate the power-down mode. The
control bits for the reduced power modes are
in the special function register PCON. Table 2
shows the state of the I/O ports during low
current operating modes.
I
The I
serial port on the 8XC552. The operation of
this subsystem is described in detail in the
8XC552 section of this manual.
Note that in both the 8XC652/4 and the
8XC552 the I
to port pins P1.6 and P1.7. Because of this,
P1.6 and P1.7 on these parts do not have a
pull-up structure as found on the 80C51.
Therefore P1.6 and P1.7 have open drain
outputs on the 8XC652/4.
2
PORT 1
C Serial Communication—SIO1
reload value range Timer 1 (in mode 2)
Data
Data
Data
Data
96 (256 – (reload value Timer 1))
2
C serial port is identical to the I
2
f
2
C-bus application.
OSC
80C652/83C652
C pins are alternate functions
Address
PORT 2
DIVIDED BY
Data
Data
Data
256
224
192
160
960
120
60
Product specification
PORT 3
Data
Data
Data
Data
2
C