DSPIC30F6010A MICROCHIP [Microchip Technology], DSPIC30F6010A Datasheet - Page 41

• Manufacturer Part Number: DSPIC30F6010A
• Description: High-Performance, 16-bit Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

5.0
The dsPIC30F6010A/6015 has 44 interrupt sources
and four processor exceptions (traps), which must be
arbitrated based on a priority scheme.
The CPU is responsible for reading the Interrupt
Vector Table (IVT) and transferring the address con-
tained in the interrupt vector to the program counter.
The interrupt vector is transferred from the program
data bus into the program counter, via a 24-bit wide
multiplexer on the input of the program counter.
The Interrupt Vector Table (IVT) and Alternate Inter-
rupt Vector Table (AIVT) are placed near the beginning
of program memory (0x000004). The IVT and AIVT
are shown in
The interrupt controller is responsible for pre-
processing the interrupts and processor exceptions,
prior to their being presented to the processor core.
The peripheral interrupts and traps are enabled,
prioritized and controlled using centralized Special
Function Registers:
• IFS0<15:0>, IFS1<15:0>, IFS2<15:0>
• IEC0<15:0>, IEC1<15:0>, IEC2<15:0>
• IPC0<15:0>... IPC11<7:0>
• IPL<3:0>
• INTCON1<15:0>, INTCON2<15:0>
© 2011 Microchip Technology Inc.
Note:
All Interrupt Request Flags are maintained in these
three registers. The flags are set by their respective
peripherals or external signals, and they are cleared
via software.
All Interrupt Enable Control bits are maintained in
these three registers. These control bits are used to
individually enable interrupts from the peripherals or
external signals.
The user assignable priority level associated with
each of these 44 interrupts is held centrally in these
twelve registers.
The current CPU priority level is explicitly stored in
the IPL bits. IPL<3> is present in the CORCON reg-
ister, whereas IPL<2:0> are present in the STATUS
register (SR) in the processor core.
Global interrupt control functions are derived from
these two registers. INTCON1 contains the control
and status flags for the processor exceptions. The
INTCON2 register controls the external interrupt
request signal behavior and the use of the alternate
vector table.
INTERRUPTS
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Programmer’s
(DS70157).
Figure
5-1.
Reference
Manual”
dsPIC30F6010A/6015
• INTTREG<15:0>
All interrupt sources can be user assigned to one of
seven priority levels, 1 through 7, via the IPCx
registers. Each interrupt source is associated with an
interrupt vector, as shown in
represent the highest and lowest maskable priorities,
respectively.
If the NSTDIS bit (INTCON1<15>) is set, nesting of
interrupts is prevented. Thus, if an interrupt is currently
being serviced, processing of a new interrupt is pre-
vented, even if the new interrupt is of higher priority
than the one currently being serviced.
Certain interrupts have specialized control bits for
features like edge or level triggered interrupts, inter-
rupt-on-change, etc. Control of these features remains
within the peripheral module which generates the
interrupt.
The DISI instruction can be used to disable the
processing of interrupts of priorities 6 and lower for a
certain number of instructions, during which the DISI bit
(INTCON2<14>) remains set.
When an interrupt is serviced, the PC is loaded with the
address stored in the vector location in program
memory that corresponds to the interrupt. There are 63
different vectors within the IVT (refer to
These vectors are contained in locations 0x000004
through 0x0000FE of program memory (refer to
Figure
and in order to preserve robustness, an address error
trap will take place should the PC attempt to fetch any
of these words during normal execution. This prevents
execution of random data as a result of accidentally
decrementing a PC into vector space, accidentally
mapping a data space address into vector space, or the
PC rolling over to 0x000000 after reaching the end of
implemented program memory space. Execution of a
GOTO instruction to this vector space will also generate
an address error trap.
The associated interrupt vector number and the
new CPU interrupt priority level are latched into
Vector number (VECNUM<5:0>) and Interrupt
level ILR<3:0> bit fields in the INTTREG register.
The new interrupt priority level is the priority of the
pending interrupt.
Note:
Note:
Note:
5-2). These locations contain 24-bit addresses,
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit. User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
Assigning a priority level of 0 to an inter-
rupt source is equivalent to disabling that
interrupt.
The IPL bits become read-only whenever
the NSTDIS bit has been set to ‘1’.
Table
5-1. Levels 7 and 1
DS70150E-page 41
Figure
5-2).