COP8SBR9 NSC [National Semiconductor], COP8SBR9 Datasheet - Page 22

• Manufacturer Part Number: COP8SBR9
• Description: 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout
• Manufacturer: NSC [National Semiconductor]

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10.0 Functional Description
10.7.1 External Reset
The RESET input when pulled low initializes the device. The
RESET pin must be held low for a minimum of one instruc-
tion cycle to guarantee a valid reset. During Power-Up ini-
(Continued)
T2CNTRL: CLEARED
T3CNTRL: CLEARED
HSTCR: CLEARED
ITMR: Cleared except Bit 6 (HSON) = 1
Accumulator, Timer 1, Timer 2 and Timer 3:
WKEN, WKEDG: CLEARED
WKPND: RANDOM
SP (Stack Pointer):
B and X Pointers:
S Register: CLEARED
RAM:
USART:
ISP CONTROL:
WATCHDOG (if enabled):
RANDOM after RESET at power-on
RANDOM after RESET
Initialized to RAM address 06F Hex
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
PSR, ENU, ENUR, ENUI: Cleared except the TBMT bit
which is set to one.
ISPADLO: CLEARED
ISPADHI: CLEARED
PGMTIM: PRESET TO VALUE FOR 10 MHz CKI
The device comes out of reset with both the WATCH-
DOG logic and the Clock Monitor detector armed, with
the WATCHDOG service window bits set and the
Clock Monitor bit set. The WATCHDOG and Clock
Monitor circuits are inhibited during reset. The
WATCHDOG service window bits being initialized high
default to the maximum WATCHDOG service window
of 64k T0 clock cycles. The Clock Monitor bit being
initialized high will cause a Clock Monitor error follow-
ing reset if the clock has not reached the minimum
specified frequency at the termination of reset. A Clock
Monitor error will cause an active low error output on
pin G1. This error output will continue until 16–32 T0
clock cycles following the clock frequency reaching the
minimum specified value, at which time the G1 output
will go high.
22
tialization, the user must ensure that the RESET pin of a
device without the Brownout Reset feature is held low until
the device is within the specified V
edge on the RESET pin while V
operating range may cause unpredictable results. An R/C
circuit on the RESET pin with a delay 5 times (5x) greater
than the power supply rise time is recommended. Reset
should also be wide enough to ensure crystal start-up upon
Power-Up.
RESET may also be used to cause an exit from the HALT
mode.
A recommended reset circuit for this device is shown in
Figure 9.
10.7.2 On-Chip Brownout Reset
When enabled, the device generates an internal reset as
V
voltage (V
the Idle Timer is preset with 00Fx (240–256 t
reaches a value greater than V
counting down. Upon underflow of the Idle Timer, the internal
reset is released and the device will start executing instruc-
tions. This internal reset will perform the same functions as
external reset. Once V
Timer time-out takes place, instruction execution begins and
the Idle Timer can be used normally. If, however, V
below the selected V
the Idle Timer is preset with 00Fx. The device now waits until
V
When enabled, the functional operation of the device, at
frequency, is guaranteed down to the V
One exception to the above is that the brownout circuit will
insert a delay of approximately 3 ms on power up or any time
the V
be held in Reset for the duration of this delay before the Idle
Timer starts counting the 240 to 256 t
soon as the V
mately 1.8V). This behavior is shown in Figure 10.
CC
CC
FIGURE 9. Reset Circuit Using External Reset
rises. While V
is greater than V
CC
drops below a voltage of about 1.8V. The device will
bor
), the device is held in the reset condition and
CC
rises above the trigger voltage (approxi-
CC
bor
CC
is less than the specified brownout
bor
, an internal reset is generated, and
is above the V
and the countdown starts over.
CC
bor
, the Idle Timer starts
CC
is below the specified
C
. This delay starts as
bor
bor
voltage. Any rising
and this initial Idle
10138912
level.
C
). When V
CC
drops
CC