COP8SBR9 NSC [National Semiconductor], COP8SBR9 Datasheet - Page 56

• Manufacturer Part Number: COP8SBR9
• Description: 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout
• Manufacturer: NSC [National Semiconductor]

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15.0 Interrupts
15.4.2.1 Programming Example: External Interrupt
WAIT:
SERVICE:
15.5 PORT L INTERRUPTS
Port L provides the user with an additional eight fully select-
able, edge sensitive interrupts which are all vectored into the
same service subroutine.
The interrupt from Port L shares logic with the wake-up
circuitry. The register WKEN allows interrupts from Port L to
be individually enabled or disabled. The register WKEDG
specifies the trigger condition to be either a positive or a
negative edge. Finally, the register WKPND latches in the
pending trigger conditions.
The GIE (Global Interrupt Enable) bit enables the interrupt
function.
A control flag, LPEN, functions as a global interrupt enable
for Port L interrupts. Setting the LPEN flag will enable inter-
rupts and vice versa. A separate global pending flag is not
needed since the register WKPND is adequate.
Since Port L is also used for waking the device out of the
HALT or IDLE modes, the user can elect to exit the HALT or
IDLE modes either with or without the interrupt enabled. If he
elects to disable the interrupt, then the device will restart
execution from the instruction immediately following the in-
struction that placed the microcontroller in the HALT or IDLE
modes. In the other case, the device will first execute the
interrupt service routine and then revert to normal operation.
(See HALT MODE for clock option wake-up information.)
15.6 INTERRUPT SUMMARY
The device uses the following types of interrupts, listed
below in order of priority:
PSW
CNTRL
RBIT
RBIT
SBIT
SBIT
SBIT
JP
.
.
.
.=0FF
VIS
.
.
.
.=01FA
.ADDRW SERVICE
.
.
.
RBIT,EXPND,PSW
.
.
.
RET I
(Continued)
=00EF
=00EE
0,PORTGC
0,PORTGD
IEDG, CNTRL
GIE, PSW
EXEN, PSW
WAIT
; G0 pin configured Hi-Z
; Ext interrupt polarity; falling edge
; Set the GIE bit
; Enable the external interrupt
; Wait for external interrupt
; The interrupt causes a
; branch to address 0FF
; The VIS causes a branch to
; interrupt vector table
; Vector table (within 256 byte
; of VIS inst.) containing the ext
; interrupt service routine
; Interrupt Service Routine
; Reset ext interrupt pend. bit
; Return, set the GIE bit
56
1. The Software Trap non-maskable interrupt, triggered by
2. Maskable interrupts, triggered by an on-chip peripheral
3. While executing from the Boot ROM for ISP or virtual E2
the INTR (00 opcode) instruction. The Software Trap is
acknowledged immediately. This interrupt service rou-
tine can be interrupted only by another Software Trap.
The Software Trap should end with two RPND instruc-
tions followed by a re-start procedure.
block or an external device connected to the device.
Under ordinary conditions, a maskable interrupt will not
interrupt any other interrupt routine in progress. A
maskable interrupt routine in progress can be inter-
rupted by the non-maskable interrupt request. A
maskable interrupt routine should end with an RETI
instruction or, prior to restoring context, should return to
execute the VIS instruction. This is particularly useful
when exiting long interrupt service routines if the time
between interrupts is short. In this case the RETI instruc-
tion would only be executed when the default VIS rou-
tine is reached.
operations, the hardware will disable interrupts from oc-
curring. The hardware will leave the GIE bit in its current
state, and if set, the hardware interrupts will occur when
execution is returned to Flash Memory. Subsequent in-
terrupts, during ISP operation, from the same interrupt
source will be lost.