LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 281

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x044
Type W1C, reset 0x0000.0000
October 09, 2007
Reset
Reset
Type
Type
Bit/Field
31:11
10
9
8
RO
RO
31
15
0
0
Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
RO
RO
30
14
0
0
reserved
reserved
Name
OEIC
BEIC
PEIC
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
W1C
W1C
W1C
Type
27
11
0
0
RO
OEIC
W1C
RO
26
10
0
0
Reset
0x00
0
0
0
BEIC
W1C
RO
25
0
9
0
Preliminary
PEIC
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Overrun Error Interrupt Clear
The OEIC values are defined as follows:
Break Error Interrupt Clear
The BEIC values are defined as follows:
Parity Error Interrupt Clear
The PEIC values are defined as follows:
W1C
RO
Value
Value
Value
24
0
8
0
reserved
0
1
0
1
0
1
Description
No effect on the interrupt.
Clears interrupt.
Description
No effect on the interrupt.
Clears interrupt.
Description
No effect on the interrupt.
Clears interrupt.
FEIC
W1C
RO
23
0
7
0
RTIC
W1C
RO
22
0
6
0
TXIC
W1C
RO
21
0
5
0
RXIC
W1C
RO
20
0
4
0
LM3S6611 Microcontroller
RO
RO
19
0
3
0
RO
RO
18
0
2
0
reserved
RO
RO
17
0
1
0
RO
RO
16
0
0
0
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