ATA5811_06 ATMEL [ATMEL Corporation], ATA5811_06 Datasheet - Page 54

• Manufacturer Part Number: ATA5811_06
• Description: UHF ASK/FSK TRANSCEIVER
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 11-5. Timing Diagram During Bit-check
54
Bit-check counter
ATA5811/ATA5812
(Lim_min = 14, Lim_max = 24)
RX_ACTIVE
Demod_Out
Bit check
T
Start-up mode
Startup_Sig_Proc
For the best noise immunity it is recommended to use a low span between T
This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A
'11111...' or a '10101...' sequence in Manchester or Bi-phase is a good choice concerning that
advice. A good compromise between sensitivity and susceptibility to noise regarding the
expected edge to edge time t
time window should be ±50% and then N
edge to edge time periods, the Bit-check limits must be programmed according to the required
span.
The Bit-check limits are determined by means of the formula below:
T
T
Lim_min is defined by the bits Lim_min 0 to Lim_min 5 in control register 5.
Lim_max is defined by the bits Lim_max 0 to Lim_max 5 in control register 6.
Using the above formulas, Lim_min and Lim_max can be determined according to the required
T
minimum edge to edge time t
limit should be set to Lim_min
Figure
Bit-check limits Lim_min = 14 and Lim_max = 24. The signal processing circuits are enabled
during T
undefined during that period. When the Bit-check becomes active, the Bit-check counter is
clocked with the cycle T
Figure 11-5
the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In
page 55
also fails if CV_Lim reaches Lim_max. This is illustrated in
Lim_min
Lim_max
Lim_min
0
11-5,
, T
= Lim_min
= (Lim_max – 1)
Startup_PLL
the Bit-check fails as the value CV_Lim is lower than the limit Lim_min. The Bit-check
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112131415161718 1 2 3 4 5 6 7 8 9 10 11
Lim_max
shows how the Bit-check proceeds if the Bit-check counter value CV_Lim is within
Figure 11-6 on page
T
XDCLK
and T
and T
T
XDCLK
XDCLK
Startup_Sig_Proc
XDCLK
T
. The time resolution defining T
XDCLK
.
ee
ee
1/2 Bit
is defined according to the section “Receiving Mode”. The lower
10. The maximum value of the upper limit is Lim_max = 63.
is a time window of ±38%, to get the maximum sensitivity the
55, and
. The output of the ASK/FSK demodulator (Demod_Out) is
Bit-check
Figure 11-7 on page 55
Bit check mode
Bit check ok
T
Bit-check
6. Using preburst patterns that contain various
1/2 Bit
Figure 11-7 on page
Lim_min
illustrate the Bit-check for the
12131415 1 2 3 4 5 6 7
and T
Bit check ok
Lim_max
Lim_min
1/2 Bit
55.
Figure 11-6 on
is T
4689F–RKE–08/06
and T
XDCLK
Lim_max
. The
.