ATA5811_06 ATMEL [ATMEL Corporation], ATA5811_06 Datasheet - Page 57

• Manufacturer Part Number: ATA5811_06
• Description: UHF ASK/FSK TRANSCEIVER
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 11-9. Receiving Mode (TMODE = 0)
4689F–RKE–08/06
Demod_Out
'0' '0' '0' '0' '0' '0' '0' '0' '0' '1'
Bit-check mode
If the TX/RX data buffer control logic detects the start bit, the data stream is written in the TX/RX
data buffer byte by byte. The start bit is part of the first data byte and must be different from the
bits of the preburst. If the preburst consists of a sequence of '00000...', the start bit must be a 1.
If the preburst consists of a sequence of '11111...', the start bit must be a 0.
If the data stream consists of more than 16 bytes, a buffer overflow occurs and the TX/RX data
buffer control logic overwrites the bytes already stored in the TX/RX data buffer. So it is very
important to ensure that the data is read in time so that no buffer overflow occurs in that case
(see
the TX/RX data buffer (see section “Transceiver Configuration”). If a byte is transferred to the
microcontroller, the counter is decremented, if a byte is received, the counter is incremented.
The counter value is available via the 4-wire serial interface.
An interrupt is issued, if the counter while counting forwards reaches the value defined by the
control bits IR0 and IR1 in control register 1.
If the TX/RX data buffer control logic detects a bit error, an interrupt is issued and the transceiver
is set back to the start-up mode (see
11-10 on page
Bit error:
Note:
Writing the control register 1, 4, 5 or 6 during receiving mode resets the TX/RX data buffer con-
trol logic and the counter which indicates the number of received bytes. If the bits OPM0 and
OPM1 are still '1' after writing to a control register, the transceiver changes to the start-up mode
(start-up signal processing).
Figure 10-1 on page
The byte consisting of the bit error will not be stored in the TX/RX data buffer. Thus it is not avail-
able via the 4-wire serial interface.
58).
a) t
b) Logical error (no edge detected in the bit center)
'0'
ee
'1'
46). There is a counter that indicates the number of received bytes in
< T
'0' '0' '0' '0'
1
1
1
0
Lim_min
1
1
1
0
0
0
0
0
Figure 11-1 on page
1
0
or T
'0' '1' '1' '1' '1' '0' '0' '1' '1' '0' '1' '0' '1' '1' '0' '0'
Receiving mode
1
0
Byte 16, Byte 32, ...
Byte 15, Byte 31, ...
Byte 14, Byte 30, ...
Byte 13, Byte 29, ...
Byte 12, Byte 28, ...
Byte 11, Byte 27, ...
Byte 10, Byte 26, ...
Byte 9, Byte 25, ...
Byte 8, Byte 24, ...
Byte 7, Byte 23, ...
Byte 6, Byte 22, ...
Byte 5, Byte 21, ...
Byte 4, Byte 20, ...
Byte 3, Byte 19, ...
Byte 2, Byte 18, ...
Byte 1, Byte 17, ...
Lim_max
< t
ee
< T
Lim_min_2T
51,
ATA5811/ATA5812
Figure 11-2 on page
or t
ee
> T
Lim_max_2T
52and
Figure
57