XR68C192 EXAR [Exar Corporation], XR68C192 Datasheet
XR68C192
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XR68C192 Summary of contents
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... DESCRIPTION The XR68C92/192 is a Dual Universal Asynchronous Receiver and Transmitter with 8 (XR68C92 (XR68C192) bytes of transmit and receive FIFOs. The XR68C92/192 is pin-to-pin and functionally compatible to the XR68C681 and Philips SCC68681 UART with additional features. The operating speed of the receiver and transmitter can be selected independently from a table of twenty four fixed baud rates, a 16X clock derived from a programmable counter/ timer external 1X or 16X clock ...
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XR68C92/192 Package Description 40 Pin DIP Package A1 1 IP3 IP1 IP0 7 R/-W 8 -DTACK 9 RXB 10 TXB 11 OP1 12 OP3 13 OP5 14 OP7 ...
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Diagram /- - - ...
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XR68C92/192 SYMBOL DESCRIPTION (* 44 TQFP Package) Symbol Pin 44 40 -DTACK A/B 35,11 31,10 TX A/B 33,13 30,11 OP0 32 29 OP1 14 12 OP2 31 28 OP3 15 13 OP4 30 27 Rev. P1.10 Signal ...
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SYMBOL DESCRIPTION (* 44 TQFP Package) Symbol Pin 44 40 OP5 16 14 OP6 29 26 OP7 17 15 A1-A4 2,4, 1,3, 40,42, 6,7 5,6 XTAL1 36 32 XTAL2 37 33 -RESET 38 34 GND 22 20 16,17 -INT 24 ...
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XR68C92/192 SYMBOL DESCRIPTION (* 44 TQFP Package) Symbol Pin 44 40 IP2 40 36 IP3 3 2 IP4 43 39 IP5 42 38 -IACK D0-D7 28,18 25,16 22,12 27,19 24,17 21,13 26,20 23,18 20,14 25,21 ...
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INTERNAL CONTROL LOGIC The internal control logic receives operation commands from the central processing unit (CPU) and generates appropriate signals to the internal sections to control device operation. The internal control logic allows ac- cess to the registers within the ...
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XR68C92/192 COMMUNICATION CHANNELS A AND B Each communication channel includes a full-duplex asynchronous receiver/transmitter (UART). The operat- ing frequency for each receiver and each transmitter can be selected independently from the baud-rate genera- tor, the C/T, or from an external ...
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RESET signal or soft-reset by programming the appro- priate command register. A hardware reset (assertion of RESET) clears the following registers: Status registers A and B (SRA and SRB) Interrupt mask register (IMR) Interrupt status register (ISR) Output port register ...
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XR68C92/192 (IPCR bit-5) is also associated with this input. IP2 This input can be used as the channel B receiver external clock input (RxBClk1), or the counter/timer external clock input. When this input functions as the external clock to the ...
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Data is trans- ferred from the transmit holding register to the transmit shift register when the shift register is idle or has completed transmission of the previous character. The transmitter ready conditions are then ...
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... A first-in first- out (FIFO) stack is used in each channels receive buffer logic and consists of 8 (16 for XR68C192) receive holding registers. The receiver buffer is composed of the FIFO and a receive shift register connected to the receiver serial- data input ...
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Connecting the request- to-send output to the clear-to-send (CTS) input of a transmitting device, prevents overrun errors in the re- ceiver. The RTS output must be manually asserted the first time. Thereafter, the receiver will control ...
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XR68C92/192 (address tag). The received character is discarded if the received address/data bit is a zero (data tag). If the receiver is enabled, all received characters are trans- ferred to the CPU by way of the receive holding register stack ...
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PROGRAMMING AND REGISTER DESCRIPTIONS READ Mode Register A (MR1A, MR2A Status Register A (SRA Reserved Receiver Buffer A (RBA) 0 ...
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XR68C92/192 Register BIT-7 [Default MRA0 [00] Watch MRB0[00] dog timer MRA1[00 MRB1[00] RTS control MRA2[00] ...
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... Force parity parity 11 = Multidrop mode MR1 A/B Bit-5. Data error mode 0 = Single Character mode 1 = Block (FIFO) mode MR1 A/B Bit-6. Receive Interrupt mode select Single character mode (RxRdy FIFO Full mode (FFULL) MR1 A/B Bit-7. Auto RTS flow control. 17 XR68C192 1 byte in FIFO 6 bytes in FIFO ...
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XR68C92/192 0 = Normal. No RTS control function Auto RTS control function MR2 A/B Mode register 2. This register is accessed after any read or write operation to MR1 A/B register is performed. Access to MR2 A/B does ...
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Baud Rate Table (based on a 3.6864MHz clock) MR0 Bits 2,0=0 CSR SET-1 A/B ACR Bit-7=0 0000 50 0001 110 0010 134.5 0011 200 0100 300 0101 600 0110 1200 0111 1050 1000 2400 1001 4800 1010 7200 1011 9600 ...
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XR68C92/192 from the receive shift register to the empty FIFO, and cleared when the CPU reads the receiver buffer, if there are no more characters in the FIFO after the read. SR A/B Bit-1. Receive FIFO Full. This bit is ...
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OP3 output select The complement of OPR C/T Output TxBClk1-Transmit B 1X clock RxBClk1- Receive B 1X clock If OP3 used for the timer ...
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XR68C92/192 programmed by MR1A Bit-6. If programmed as receiver ready copy of the SRA Bit-0. If programmed as FIFO full copy of the SRA Bit-1. ISR Bit-2. Channel A change in break. This bit ...
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IPR Bit-7. Not used and set to “0”. COUNTER REGISTER (CUR and CLR) The count upper register (CUR) and count lower register (CLR) hold the most-significant byte and the least-significant byte, respectively, of the current counter value. These registers should ...
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XR68C92/192 AC ELECTRICAL CHARACTERISTICS T =0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. A Symbol Parameter T T Clock pulse duration 1w Oscillator/Clock frequency 3w T Address ...
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... V Output high level OH I Input leakage IL I Clock leakage CL I Avg power supply current CC XR68C92 I Avg stand by supply current SB Typ.@ XR68C192 I Avg stand by supply current SB o Typ.@ Input capacitance P Rev. P1.10 XR68C92/192 GND - 0 VCC +0.3 V Limits Limits Units 3.3 5.0 Min Max ...
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XR68C92/192 /- /- Figure ...
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ENABLE -RxRDY -FFULL -RxRDY/ -FFULL -CS Status Data (D1) OVERRUN ERROR -RTS ENABLE -TxRDY R/-W -CTS -RTS Rev. P1. D10 Status Data D11 Will be lost due to overrun Figure 3: ...
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XR68C92/192 IP6-IP0 T9s -CS R/-W OP7-OP0 R/-W -CS -INT ExCLK Rev. P1.10 T9h Figure 5: Input Port Timing T10d Old Data Figure 6: Output Port Timing T11d T11d Figure 7: Interrupt Timing T1w T2w T3w Figure 8: External clock Timing ...
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LEAD PLASTIC DUAL-IN-LINE Seating Plane L B INCHES SYMBOL Note: The control dimension is the inch column Rev. P1.10 XR68C92/192 (600 MIL ...
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XR68C92/192 44 LEAD PLASTIC LEADED CHIP CARRIER SYMBOL Note: The control dimension is the inch column Rev. P1.10 (PLCC) Rev. 1.00 D ...
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LEAD THIN QUAD FLAT PACK ( 1.4 mm, TQFP Seating Plane A 1 INCHES SYMBOL Note: The control dimension is the ...
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XR68C92/192 EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license ...