XR17L154CV EXAR [Exar Corporation], XR17L154CV Datasheet

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AUGUST 2003 GENERAL DESCRIPTION 1 The XR17L154 (L154 quad PCI Bus Universal Asynchronous Receiver and Transmitter (UART) with same package and pin-out as the Exar XR17C158 octal UART. The device is designed to meet today’s 32-bit PCI Bus ...

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... AD28 141 AD27 142 AD26 143 144 AD25 ORDERING INFORMATION ART UMBER ACKAGE XR17L154CV 144-Lead TQFP XR17L154IV 144-Lead TQFP -40°C to +85°C XR17L154 144-TQFP O PERATING T EMPERATURE R ANGE 0°C to +70°C Discontinued. See XR17D154CV for a replacement. Discontinued. See XR17D154IV for a replacement. ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 PIN DESCRIPTIONS AME IN YPE PCI LOCAL BUS INTERFACE RST# 134 CLK 135 AD31-AD0 138-144 6-13 26-33 37-44 FRAME# 15 2,14,25,36 - C/BE3# C/BE0# IRDY# 16 ...

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DISCONTINUED PIN DESCRIPTIONS AME IN RX1 99 RTS1# 104 CTS1# 100 DTR1# 105 DSR1# 101 CD1# 102 RI1# 103 TX2 88 RX2 81 RTS2# 86 CTS2# 82 DTR2# 87 DSR2# 83 CD2# ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 PIN DESCRIPTIONS AME IN YPE MPIO3 73 I/O MPIO4 68 I/O MPIO5 67 I/O MPIO6 66 I/O MPIO7 65 I/O EECK 116 EECS 115 EEDI 114 EEDO 113 ...

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DISCONTINUED FUNCTIONAL DESCRIPTION The XR17L154 (L154) integrates the functions of 4 enhanced 16550 UARTs with the PCI Local Bus interface and a non-volatile memory interface for PCI bus’s plug-and-play auto-configuration, a 16-bit timer/counter, 8 multi-purpose inputs/outputs, ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 1.0 XR17L154 REGISTERS The XR17L154 UART has three different sets of registers as shown in configuration space registers are for plug-and-play auto-configuration when connecting the device to the PCI bus. This auto-configuration ...

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DISCONTINUED T 1: PCI L ABLE DDRESS ITS YPE 0x00 31:16 1 Device ID (Exar device ID number or from EEPROM) RWR 15:0 1 Vendor ID (Exar ID or from EEPROM) specified by ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1 PCI L ABLE DDRESS ITS YPE 15:0 1 Subsystem Vendor ID (write from external EEPROM by cus- RWR tomer) 0x30 31:0 RO Expansion ROM Base Address (Unimplemented) ...

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DISCONTINUED T 2: XR17L154 D ABLE FFSET DDRESS EMORY 0x000 - 0x00F UART channel 0 Regs 0x010 - 0x07F Reserved 0x080 - 0x093 DEVICE CONFIG. REGISTERS 0x094 - 0x0FF Reserved 0x100 UART ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1 ABLE EVICE A DDRESS R EGISTER [A7:A0] Ox080 INT0 [7:0] Ox081 INT1 [15:8] Ox082 INT2 [23:16] Ox083 INT3 [31:24] Ox084 TIMERCNTL Ox085 TIMER Ox086 TIMERLSB Ox087 TIMERMSB Ox088 8XMODE ...

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DISCONTINUED ABLE EVICE A R DDRESS EGISTER - INTERRUPT (read-only) 0x080 083 0x084-087 TIMER (read/write) 0x088-08B ANCILLARY1 (read/write) 0x08C-08F ANCILLARY2 (read-only) 0x090-093 MPIO (read/write) 1.2.1 The Interrupt Status Register The XR17L154 has a ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 Registers INT3, INT2 and INT1 [32:8] Twenty four bit encoded interrupt indicator. Each channel’s interrupt is encoded into 3 bits for receive, transmit, and status. Bit [10:8] represent channel 0 and go ...

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DISCONTINUED T ABLE RXRDY is clear by reading data in the RX FIFO until it falls below the trigger level. RXRDY Time-out interrupt is cleared when the RX FIFO becomes empty. RX Line Status interrupt clears ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 B it TIMER [15:8] - (default 0x00) Reserved. TIMERMSB [31:24] and TIMERLSB [23:16] TIMERMSB and TIMERLSB form a 16-bit value. The least-significant bit of the timer is ...

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DISCONTINUED 1.2.6 SLEEP [31:24] - (default 0x00) The first four bits of the Sleep register enables each UART channel separately to enter Sleep mode. The upper bits are reserved. Sleep mode reduces power ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 1.2.9 Multi-Purpose Inputs and Outputs The L154 provides 8 multi-purpose inputs/outputs [MPIO7:0] for general use. Each pin can be programmed input or output function. The input logic state can ...

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DISCONTINUED MPIOINT [7:0] - (default 0x00) Enable multipurpose input pin interrupt. If the pin is selected by MPIOSEL as input then bit-0 enables input pin 0 for interrupt, and bit-7 enables input pin 7. No interrupt ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 MPIOSEL [7:0] - (default 0xFF) Multipurpose input/output pin select. This register defines the functions of the pins. A logic 1 (default) defines the pin for input and a logic "0" for output. ...

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DISCONTINUED 3.1 FIFO DATA LOADING AND UNLOADING THROUGH THE DEVICE CONFIGURATION REGISTERS IN 32-BIT FORMAT. The transmit and receive data registers are defined for channel 0 to channel 3 with each channel having it’s own address ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1 FIFO, EAD B YTE E WITH LSR RRORS Read n+0 to n+1 FIFO Data n+1 Read n+2 to n+3 FIFO Data n+3 Etc Channel Receive Data with ...

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DISCONTINUED 4.1 Programmable Baud Rate Generator Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The prescaler is controlled by a software bit in the MCR register. The ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1 ABLE YPICAL DATA RATES WITH A O Data Rate O Data Rate UTPUT UTPUT MCR Bit-7=1 MCR Bit-7=0 100 400 600 2400 1200 4800 2400 9600 4800 19.2k 9600 ...

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DISCONTINUED RTS/DTR CTS/DSR F IGURE UTO AND Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 CTSB# 3 TXB ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 4.3 Infrared Mode Each UART in the L154 includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The input pin ENIR conveniently activates all 4 UART ...

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DISCONTINUED 4.4 Internal Loopback Each UART channel provides an internal loopback capability for system diagnostic. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 Address lines select the 16 registers in each channel. The first 8 registers are 16550 compatible with the EXAR enhanced feature registers located on next 8 addresses locations. Addresses ...

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DISCONTINUED T 11: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A3- AME RITE RHR R Bit THR ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 T 11: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A3- AME RITE XCHAR ...

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DISCONTINUED 4.6.3 Transmitter Operation in FIFO The host may fill the transmit FIFO with bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 4.7.1 Receiver Operation in non-FIFO Mode F 14 IGURE ECEIVER PERATION IN NON ...

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DISCONTINUED Baud Rate Generator Divisors (DLL and DLM) The Baud Rate Generator (BRG 16-bit counter that generates the data rate for the transmitter and receiver. The rate is programmed through registers DLL and DLM ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 IER[3]: Modem Status Interrupt Enable Logic 0 = Disable the modem status register interrupt (default). Logic 1 = Enable the modem status register interrupt. IER[4]: Reserved. IER[5]: Xoff Interrupt Enable (requires EFR ...

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DISCONTINUED RTS#/DTR# output status change interrupt is cleared by a read to the ISR register. CTS#/DSR# input status change interrupt is cleared by a read to the MSR register ABLE P ISR R RIORITY ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 FCR[2]: TX FIFO Reset This bit is only active when FCR bit-0 is active. Logic transmit FIFO reset (default). Logic 1 = Reset the transmit FIFO pointers and FIFO ...

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DISCONTINUED T 13: T ABLE RANSMIT AND FCTR FCTR FCR FCR FCR ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT LCR[3]: TX and RX ...

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DISCONTINUED LCR[7]: Baud Rate Divisors Enable Baud rate generator divisor (DLL/DLM) enable. Logic 0 = Data registers are selected. (default) Logic 1 = Divisor latch registers are selected. Modem Control Register (MCR) The MCR register is ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 MCR[7]: Clock Prescaler Select Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable Baud Rate Generator without further modification, i.e., ...

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DISCONTINUED LSR[7]: Receive FIFO Data Error Flag Logic FIFO error (default). Logic indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 MSR[7]: CD Input Status CD# (active high, logical 1). Normally this bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR ...

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DISCONTINUED FCTR [3:0] - Auto RTS/DTR Flow Control Hysteresis Select These bits select the auto RTS/DTR flow control hysteresis and only valid when TX and RX Trigger Table-D is selected (FCTR bit-6 and 7 are set ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 FCTR[7:6]: TX and RX FIFO Trigger Table Select These 2 bits select the transmit and receive FIFO trigger level table When table ...

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DISCONTINUED EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables the functions in IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5 modified. After modifying any enhanced ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 TXCNT[7:0]: Transmit FIFO Level Counter, read-only Transmit FIFO level byte count from 0x00 (zero) to 0x40 (64). This 8-bit register gives an indication of the number of characters in the transmit FIFO. ...

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DISCONTINUED T ABLE REGISTERS TXCNT TXTRG RXCNT RXTRG XCHAR XOFF1 XOFF2 I/O SIGNALS TX[ch-3:0] IRTX[ch-3:0] RTS#[ch-3:0] DTR#[ch-3:0] 18: UART[3:0] RESET CONDITIONS RESET STATE DLL Bits 7-0 = 0xXX DLM Bits 7-0 = 0xXX RHR Bits 7-0 ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation Thermal Resistance (20x20x1.0mm 144-TQFP) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS FOR 3.3V SIGNALLING ...

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DISCONTINUED AC ELECTRICAL CHARACTERISTICS FOR 3.3V SIGNALING TA (-40 to +85 C for industrial grade package), Vcc = 3.3V +/-10% unless otherwise specified YMBOL ARAMETER CLK PCI ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 F 16. PCI B C IGURE US ONFIGURATION ost ost A D[31:0] H ost /BE [3:0]# H ost IR ...

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DISCONTINUED F 17 IGURE EVICE ONFIGURATION AND CLK Host FRAME# Host AD[31:0] Address Host Target Bus C/BE[3:0]# Byte Enable# = BYTE CMD Host IRDY# Host TRDY# Target DEVSEL# Target Address PAR ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1 IGURE EVICE ONFIGURATION REGISTERS TION CLK FRAM ata AD[31:0] A ddress ...

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DISCONTINUED F 19 IGURE EVICE ONFIGURATION CLK H ost 1 FRAM E# H ost AD[31: ost Target Bus C/BE[3:0]# Byte Enab le ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 F 20. PCI B C (DC IGURE US LOCK TO 1.44 ns (max) CLK Tvalid (2-11 ns) Bused Signal Output Delay Ton (2 ns min) Tri-State Output Bused Signal Input 33MH ) ...

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DISCONTINUED F 21 IGURE RANSMIT ATA NTERRUPT AT START BIT TX Data TX Interrupt at Transmit Trigger Level F 22 IGURE ECEIVE ATA EADY NTERRUPT AT START BIT RX ...

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XR17L154 3.3V PCI BUS QUAD UART REV. 1.1.0 PACKAGE DIMENSIONS DISCONTINUED 55 áç áç áç áç ...

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XR17L154 DISCONTINUED REVISION HISTORY D R ATE EVISION August 2002 Adv. Rev. 1.0.0 October 2002 Rev. 1.0.0 August 2003 Rev. 1.1.0 EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve ...