ISPPAC-CLK5610V-01T100C LATTICE [Lattice Semiconductor], ISPPAC-CLK5610V-01T100C Datasheet - Page 17

• Manufacturer Part Number: ISPPAC-CLK5610V-01T100C
• Description: In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
M, N, and V Dividers
The ispClock5600 incorporates a set of programmable dividers which provide the ability to synthesize output fre-
quencies differing from that of the reference clock input.
The input, or M divider prescales the input reference frequency, and can be programmed with integer values over
the range of 1 to 32. To achieve low levels of output jitter, it is best to use the smallest M divider value possible.
The feedback, or N divider prescales the feedback frequency and like the M divider, can also be programmed with
integer values ranging from 1 to 32.
Each one of the five output, or V dividers can be independently programmed to provide even division ratios ranging
from 2 to 64.
When the PLL is selected (PLL_BYPASS=LOW) and locked, the output frequency of each V divider (f
culated as:
where
Note that because the feedback may be taken from any V divider, V
Because the VCO has an operating frequency range spanning 320 MHz to 640 MHz, and the V dividers provide
division ratios from 2 to 64, the ispClock5600 can generate output signals ranging from 5MHz to 320 MHz. For per-
formance and stability reasons, however, there are several constraints which should be followed when selecting
divider values:
Output Duty Cycle
The ispClock5600’s output duty cycle varies as a function of the V divider used to generate that output. If the V-
divider setting is either 2 or a multiple of 4, the nominal output duty cycle will be exactly 50%. All other V divider set-
tings will result in non-50% output duty cycles. Table 3 summarizes the nominal output duty cycle as a function of
the V divider setting. Note that if the output is inverted, the duty cycle will be equal to 100%-DC%, where DC% is
the duty cycle indicated in the table. For example, with a V divider of 14, the non-inverted duty cycle from Table 3
will be 43%. For an inverted output, the duty cycle will be 100%-43% or 57%.
f
f
M and N are the input and feedback divider settings
V
V
• Use the smallest feasible value for the M divider
• The output frequency from the M (and N) divider should be greater or equal to 10 MHz.
• The product of the N divider and the V divider used to close the PLL’s feedback loop should be less than or
k
ref
fbk
k
equal to 64 (N x V
is the frequency of V divider k
is the setting of the V divider used to provide output k
is the input reference frequency
is the setting of the V divider used to close the PLL feedback path
fbk
≤ 64)
f
k
=
f
ref
17
N x V
M x V
fbk
k
k
and V
ispClock5600 Family Data Sheet
fbk
may refer to the same divider.
k
) may be cal-
(1)