ISPPAC-CLK5610V-01T100C LATTICE [Lattice Semiconductor], ISPPAC-CLK5610V-01T100C Datasheet - Page 19

• Manufacturer Part Number: ISPPAC-CLK5610V-01T100C
• Description: In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Table 4. REFSEL and FBKSEL Operation for ispClock5620
Each input also features internal programmable termination resistors, as shown in Figure 13. Note that all refer-
ence inputs (REFA+, REFA-, REFB+, REFB-) terminate to the REFVTT pin, while all feedback inputs (FBKA+,
FBKA-, FBKB+, FBKB-) terminate to the FBKVTT pin.
Figure 13. ispClock5600 Clock Reference and Feedback Input Structure (REFA+/- Pair Shown)
The following usage guidelines are suggested for interfacing to supported logic families.
LVTTL (3.3V), LVCMOS (1.8V, 2.5V, 3.3V)
The receiver should be set to LVCMOS or LVTTL mode, and the input signal should be connected to the ‘+’ termi-
nal of the input pair (e.g. REFA+). The ‘-’ input terminal should be left floating. CMOS transmission lines are gener-
ally source terminated, so all termination resistors should be set to the OPEN state. Figure 14 shows the proper
configuration. Please note that because switching thresholds are different for LVCMOS running at 1.8V, there is a
separate configuration setting for this particular standard.
• LVTTL (3.3V)
• LVCMOS (1.8V, 2.5V, 3.3V)
• SSTL2
• SSTL3
• HSTL
• Differential SSTL2
• Differential SSTL3
• Differential HSTL
• LVDS
• LVPECL (differential, 3.3V)
REFVTT
REFA+
REFA-
ispClock5600
R
T
REFSEL
0
1
R
T
Input Pair
Selected
REFB+/-
REFA+/-
Single-ended
Differential
19
Receiver
Receiver
FBKSEL
0
1
ispClock5600 Family Data Sheet
Input Pair
Selected
FBKA+/-
FBKB+/-
To Internal
Logic