LTM8020EV-PBF LINER [Linear Technology], LTM8020EV-PBF Datasheet - Page 8

• Manufacturer Part Number: LTM8020EV-PBF
• Description: 200mA, 36V DC/DC ?Module
• Manufacturer: LINER [Linear Technology]

LTM8020
APPLICATIONS INFORMATION
For most applications, the design process is straight
forward, summarized as follows:
1. Look at Table 1 and fi nd the row that has the desired
2. Apply the C
While these component combinations have been tested for
proper operation, it is incumbent upon the user to verify
proper operation over the intended system’s line, load and
environmental conditions.
If an output voltage other than those listed in Table 1 is
desired, use the equation R
where R
C
output voltage that most closely matches the intended
application, and verify proper operation over the system’s
line, load and environmental conditions.
Capacitor Selection Considerations
The C
minimum recommended values for the associated oper-
ating conditions. Applying capacitor values below those
indicated in Table 1 is not recommended, and may result
in undesirable operation. An input system bulk capacitor
is assumed. Using larger values is generally acceptable,
and can yield improved dynamic response, if it is neces-
sary. Again, it is incumbent upon the user to verify proper
operation over the intended system’s line, load and envi-
ronmental conditions.
Ceramic capacitors are small, robust and have very low
ESR. However, not all ceramic capacitors are suitable.
X5R and X7R types are stable over temperature and ap-
plied voltage and give dependable service. Other types,
including Y5V and Z5U have very large temperature and
voltage coeffi cients of capacitance. In an application cir-
cuit they may have only a small fraction of their nominal
capacitance resulting in much higher output voltage ripple
than expected.
Ceramic capacitors are also piezoelectric. The LTM8020’s
switching frequency depends on the load current, and
at light loads it can excite a ceramic capacitor at audio
8
IN
input range and output voltage.
on that row.
and C
IN
ADJ
and C
OUT
is in kΩ. As a starting point, use values for
IN
that correspond to the input voltage and
, C
OUT
OUT
capacitor values in Table 1 are the
, R
ADJ
and BIAS connection indicated
ADJ
= 623.75/(V
OUT
– 1.25),
frequencies, generating audible noise. Since the LTM8020
operates at a lower current limit during Burst Mode opera-
tion, the noise is typically very quiet to a casual ear.
If this audible noise is unacceptable, use a high performance
electrolytic capacitor at the output. The input capacitor can
be a parallel combination of a 2.2μF ceramic capacitor and
a low cost electrolytic capacitor.
A fi nal precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LTM8020. A
ceramic input capacitor combined with trace or cable
inductance forms a high Q (under damped) tank circuit.
If the LTM8020 circuit is plugged into a live supply, the
input voltage can ring to twice its nominal value, possi-
bly exceeding the device’s rating. This situation is easily
avoided; see the Hot-Plugging Safely section.
Shorted Input Protection
Care needs to be taken in systems where the output will
be held high when the input to the LTM8020 is absent.
This may occur in battery charging applications or in
battery backup systems where a battery or some other
supply is diode OR’ed with the LTM8020’s output. If the
V
(either by a logic signal or because it is tied to V
the LTM8020’s internal circuitry will pull its quiescent
current through its SW pin. This is fi ne if your system
can tolerate a few milli-amps in this state. If you ground
the SHDN pin, the SW pin current will drop to essentially
zero. However, if the V
is held high, then parasitic diodes inside the LTM8020
can pull large currents from the output through the SW
pin and the V
only when the input voltage is present and that protects
against a shorted or reversed input.
Figure 2. Diode D1 Prevents a Shorted Input from Discharging
a Backup Battery Tied to the Output, as Well as Protecting the
LTM8020 from a Reversed Input
IN
pin is allowed to fl oat and the SHDN pin is held high
IN
V
pin. Figure 2 shows a circuit that will run
IN
1M
IN
100k
D1
pin is grounded while the output
V
SHDN
IN
LTM8020
GND
8020 F02
IN
), then
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