ISPLSI2032-110LJI LATTICE [Lattice Semiconductor], ISPLSI2032-110LJI Datasheet - Page 2

• Manufacturer Part Number: ISPLSI2032-110LJI
• Description: In-System Programmable High Density PLD
• Manufacturer: LATTICE [Lattice Semiconductor]

Figure 1. ispLSI 2032/A Functional Block Diagram
The devices also have 32 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock
(Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the ORP. Each ispLSI
2032 and 2032A device contains one Megablock.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
Functional Block Diagram
SDO/IN 1
GOE 0
SDI/IN 0
Notes:
MODE
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
ispEN
*Y1 and RESET are multiplexed on the same pin
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
A1
A2
A3
A0
Global Routing Pool
(GRP)
2
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2032 and 2032A devices are se-
lected using the dedicated clock pins. Three dedicated
clock pins (Y0, Y1, Y2) or an asynchronous clock can be
selected on a GLB basis. The asynchronous or Product
Term clock can be generated in any GLB for its own clock.
Specifications ispLSI 2032/A
*Y1/RESET
SCLK/Y2
Y0
A6
A5
A4
A7
0139B(1)isp/2000
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16