ISPLSI2032-110LJI LATTICE [Lattice Semiconductor], ISPLSI2032-110LJI Datasheet - Page 6

• Manufacturer Part Number: ISPLSI2032-110LJI
• Description: In-System Programmable High Density PLD
• Manufacturer: LATTICE [Lattice Semiconductor]

1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
PARAMETER
t
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
External Timing Parameters
pd1
pd2
max
max (Ext.)
max (Tog.)
su1
co1
h1
su2
co2
h2
r1
rw1
ptoeen
ptoedis
goeen
goedis
wh
wl
COND.
TEST
A
A
A
A
A
B
C
B
C
–
–
–
–
–
–
–
–
–
–
4
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
#
1
2
3
4
5
6
7
8
9
2
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
Over Recommended Operating Conditions
DESCRIPTION
6
Specifications ispLSI 2032/A
1
3
(
tsu2 + tco1
1
)
MIN.
77.0
125
111
5.5
0.0
7.5
0.0
6.5
4.0
4.0
–
–
–
–
–
–
–
–
–
-110
MAX.
10.0
13.0
13.5
14.5
14.5
5.5
6.5
7.0
7.0
–
–
–
–
–
–
–
–
–
–
MIN.
84.0
57.0
83.0
10.0
7.5
0.0
9.5
0.0
6.0
6.0
–
–
–
–
–
–
–
–
–
-80
Table 2-0030B-110/2032
MAX.
15.0
18.5
19.5
24.0
24.0
12.0
12.0
8.0
9.5
–
–
–
–
–
–
–
–
–
–
UNITS
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns