SAK-C504 Infineon Technologies AG, SAK-C504 Datasheet
SAK-C504
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SAK-C504 Summary of contents
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... Edition 2000-05 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2000. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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C504 ...
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C504 Revision History: Previous Version: Page Subjects (major changes since last revision OTP Memory Operation is added. 41 Table on Version Byte Content is added Characteristics of Programming Mode is added. V several ...
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Single-Chip Microcontroller C500 Family C504 • Fully compatible to standard 8051 microcontroller • MHz external operating frequency • 16 Kbyte on-chip program memory – C504-2R: ROM version (with optional ROM protection) – C504-2E: programmable OTP version ...
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... Microcontrollers” which summarizes all available microcontroller variants. Note: The ordering codes for the Mask-ROM versions are defined for each product after verification of the respective ROM code. Data Sheet SAF-C504 T : – SAK-C504 : – 125 C A (max. operating frequency: 24 MHz) 2 C504 ) TM 2000-05 ...
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V AREF V AGND XTAL1 XTAL2 RESET EA ALE PSEN CTRAP COUT3 Figure 2 Logic Symbol Data Sheet Port 0 8-Bit Digital I/O Port 1 8-Bit Digital I/O/ 4-Bit Analog Inputs C504 Port 2 8-Bit Digital ...
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P0.3 / AD3 P0.2 / AD2 P0.1 / AD1 P0.0 / AD0 V AREF V GND P1.0 / AN0 / T2 P1.1 / AN1 / T2EX P1.2 / AN2 / CC0 P1.3 / AN3 / COUT0 P1.4 / CC1 Figure ...
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Table 1 Pin Definitions and Functions Symbol Pin Number (P-MQFP-44) P1 RESET 4 Data Sheet 1) I/O Function I/O Port 8-bit ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number (P-MQFP-44) P3 Data Sheet 1) I/O Function I/O Port 8-bit bidirectional port. P3.0 ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number (P-MQFP-44) CTRAP 6 XTAL2 14 XTAL1 15 P2.0 - P2.7 18-25 Data Sheet 1) I/O Function I CCU Trap Input With CTRAP = low, the compare outputs of the CAPCOM ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number (P-MQFP-44) PSEN 26 ALE 27 COUT3 P0 AREF Data Sheet 1) I/O Function O The Program Store Enable output is ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number (P-MQFP-44 AGND Input Output Data Sheet 1) I/O Function – Reference ground for the A/D converter. – ...
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V DD Oscillator Watchdog V SS XTAL1 OSC & Timing XTAL2 CPU RESET ALE Timer 0 PSEN EA Timer 1 Timer 2 Interrupt Unit USART COUT3 Capture/Compare Unit CTRAP V AREF A/D Converter 10-Bit V AGND S & H Figure ...
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CPU The C504 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting ...
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Memory Organization The C504 CPU manipulates operands in the following four address spaces: – Kbyte of program memory: 16K ROM for C504-2R – Kbyte of external data memory – 256 bytes of internal data ...
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Reset and System Clock Operation The reset input is an active high input. An internal Schmitt trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held high for at ...
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Figure 7 shows the recommended oscillator circuit for the C504, while Figure 8 shows the circuit for using an external clock source. Figure 7 Recommended Oscillator Circuit External Clock Signal Figure 8 External Clock Source Data Sheet C XTAL2 3.5 ...
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Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of ...
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Special Function Registers All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 63 special function registers (SFR) include pointers and registers that provide an interface between the CPU ...
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Table 2 Special Function Registers - Functional Blocks Block Symbol Name CPU ACC Accumulator B B-Register DPH Data Pointer, High Byte DPL Data Pointer, Low Byte PSW Program Status Word Register SP Stack Pointer System Control Register SYSCON Interrupt IEN0 ...
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Table 2 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Timer 2 T2CON Timer 2 Control Register T2MOD Timer 2 Mode Register RC2H Timer 2 Reload Capture Register, High Byte RC2L Timer 2 Reload Capture Register, Low Byte ...
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Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses Addr Register Content after 1) Reset DPL DPH ...
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Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr Register Content after 1) Reset 2)3) B0 P3ANA XX11- H 11XX B B1 SYSCON XX10- H XXX0 B 2) ...
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Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr Register Content after 1) Reset 2) D0 PSW CP2L CP2H XXXX. H XX00 B D4 CMP2L 00 ...
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Timer/Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4. Table 4 Timer/Counter 0 and 1 Operating Modes Mode Description 0 8-bit timer/counter with a divide-by-32 prescaler 1 16-bit timer/counter ...
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Timer/Counter 2 Timer 16-bit Timer/Counter with an up/down count feature. It can operate either as a timer event counter. This is selected by bit C/ operating modes as shown in Table 5. Table 5 ...
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Capture/Compare Unit The Capture/Compare Unit (CCU) of the C504 consists of a 16-bit 3-channel capture/ compare unit (CAPCOM) and a 10-bit 1-channel compare unit (COMP). In compare mode, the CAPCOM unit provides two output signals per channel, which can have ...
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The Compare Timers 1 and 2 are free running, processor clock coupled 16-bit / 10-bit timers; each of which has a count rate with a maximum of f compare timer operations with its possible compare output signal waveforms are shown ...
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Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in Table 6. The possible baud rates can be calculated using the formulas given in Table 6. ...
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The possible baud rates can be calculated using the formulas given in Table 7. Table 7 Formulas for Calculating Baud Rates Source of Operating Mode Baud Rate Oscillator 0 2 Timer 1 (16-bit timer (8-bit timer with 1, ...
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A/D Converter The C504 has a high performance 8-channel 10-bit A/D converter using successive approximation technique for the conversion of analog input voltages. Figure 14 shows the block diagram of the A/D Converter. Port 1/3 Clock f /2 Prescaler ...
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The A/D Converter uses two clock signals for operation: the conversion clock and the input clock ADC IN clock f which is applied at the XTAL pins. The duration of an A/D conversion is a OSC multiple ...
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Interrupt System The C504 provides 12 interrupt sources with two priority levels. Figures 16 and 17 give a general overview of the interrupt sources and illustrate the interrupt request and control flags. Figure 16 Interrupt Request Sources (Part 1) Data ...
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P3.6/WR/INT2 IT2 ITCON.7 P1.2/AN2/CC0 P1.4/CC1 P1.6/CC2 Compare Timer 1 Interrupt Compare Timer 2 Interrupt CCU Emergency Interrupt Bit addressable Request Flag is cleared by hardware Figure 17 Interrupt Request Sources (Part 2) Data Sheet < IE2 ITCON.6 EX2 ...
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Table 8 Interrupt Vector Addresses Request Flags IE0 TF0 IE1 TF1 TF2 + EXF2 IADC IE2 TRF, BCERR CT2P CC0F-CC2F, CC0R-CC2R CT1FP, CT1FC – A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not ...
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Fail Save Mechanisms The C504 offers enhanced fail save mechanisms, which allow an automatic recovery from software or hardware failure. – a programmable 15-bit Watchdog Timer – Oscillator Watchdog Programmable Watchdog Timer The Watchdog Timer in the C504 is a ...
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Oscillator Watchdog The Oscillator Watchdog of the C504 serves for three functions: – Monitoring of the on-chip oscillator’s function The watchdog supervises the on-chip oscillator's frequency lower than the frequency of an auxiliary RC oscillator, the internal ...
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Figure 19 Block Diagram of the Oscillator Watchdog Power Saving Modes The C504 provides two power saving modes, the idle mode and the power down mode. – In the idle mode, the oscillator of the C504 continues to run, but ...
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Table 10 Power Saving Modes Overview Mode Entering (2-Instruction Example) Idle mode ORL PCON, #01H ORL PCON, #20H Power With external wake-up Down mode capability from power down enabled ORL SYSCON,#10H ORL PCON1,#80H ANL SYSCON,#0EFH ORL PCON,#02H ORL PCON,#40H With ...
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OTP Memory Operation (C504-2E only) The C504-2E is the OTP version of the C504 microcontroller with a 16Kbyte one-time programmable (OTP) program memory. Fast programming cycles are achieved (1 byte in 100 s) with the C504-2E. Several levels of OTP ...
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Pin Configuration in Programming Mode N.C. N.C. N.C. N.C. N.C. N.C. N.C. Figure 21 Pin Configuration of the C504-2E in Programming Mode (top view) Data Sheet ...
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Pin Definitions Table 11 contains the functional description of all C504-2E pins which are required for OTP memory programming. Table 11 Pin Definitions and Functions of the C504-2E in Programming Mode Symbol Pin No. P-MQFP-44 RESET 4 PMSEL0 5 PMSEL1 ...
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Table 11 Pin Definitions and Functions of the C504-2E in Programming Mode (cont’d) Symbol Pin No. P-MQFP-44 XTAL1 P2 P2.7 PSEN 26 PROG P0.7 ...
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Programming Mode Selection The selection for the OTP programming mode can be separated into two different parts: – Basic programming mode selection – Access mode selection With basic programming mode selection, the device is put into the mode in which ...
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Table 12 Access Modes Selection Access Mode Program OTP memory byte Read OTP memory byte Program OTP lock bits Read OTP lock bits Read OTP version byte Lock Bits Programming / Read The C504-2E has two programmable lock bits which, ...
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Version Bytes The C504-2E and C504-2R provide three version bytes at mapped address locations and FE . The information stored in the version bytes, is defined by the mask each microcontroller step. ...
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... V pins with respect to ground ( DD the absolute maximum ratings. Operating Conditions Parameter Supply voltage Ground voltage Ambient temperature SAB-C504 SAF-C504 SAK-C504 Analog reference voltage Analog ground voltage Analog input voltage CPU clock Data Sheet Symbol Limit Values min. T – – ...
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Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C504 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column ...
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DC Characteristics (cont’d) (Operating Conditions apply) Parameter Output high voltage (Port 0 in external bus mode, ALE, PSEN) Logic 0 input current (Ports Logical 1-to-0 transition current (Ports Input leakage current (Port 0, EA) ...
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Notes: 1) Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the and Port 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when ...
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DD max typ max typ Figure 23 IDD Diagram Data Sheet C504- ...
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Power Supply Current Calculation Formulas Parameter Active mode C504-2R C504-2E Idle mode C504-2R C504-2E f Note: is the oscillator frequency in MHz. osc A/D Converter Characteristics (Operating Conditions apply) Parameter Symbol V Analog input voltage Sample time t t Conversion ...
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Clock Calculation Table Clock Prescaler ADCL1, 0 Ratio Further timing conditions: Notes may exceed AIN AGND AREF cases will be X000 or X3FF During ...
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AC Characteristics for C504-L / C504-2R / C504-2E (Operating Conditions apply for Port 0, ALE and PSEN outputs = 100 pF; L Parameter Program Memory Characteristics ALE pulse width Address setup to ALE Address hold after ALE ALE ...
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AC Characteristics for C504-L / C504-2R / C504-2E (cont’d) Parameter External Data Memory Characteristics RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid ...
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AC Characteristics for C504-L24 / C504-2R24 / C504-2E24 (Operating Conditions apply for Port 0, ALE and PSEN outputs = 100 pF; L Parameter Program Memory Characteristics ALE pulse width Address setup to ALE Address hold after ALE ALE ...
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AC Characteristics for C504-L24 / C504-2R24 / C504-2E24 (cont’d) Parameter External Data Memory Characteristics RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid ...
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... PSEN Address valid after PSEN Address to valid instr in Address float to PSEN Notes: 1) SAK-C504 is not specified for 40 MHz operation. 2) Interfacing the C504 to devices with float times permissible. This limited bus contention will not cause any damage to Port 0 drivers. Data Sheet 1) ...
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AC Characteristics for C504-L40 / C504-2R40 / C504-2E40 (cont’d) Parameter External Data Memory Characteristics RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid ...
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ALE PSEN Port 0 Port 2 Figure 24 Program Memory Read Cycle ALE PSEN RD t AVLL from Port DPL Port 2 Figure 25 Data Memory Read Cycle Data Sheet t LHLL t t ...
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ALE PSEN WR t AVLL from Port DPL t Port 2 Figure 26 Data Memory Write Cycle V - 0.5V DD 0 0.1 DD 0.45V Figure 27 External Clock Cycle ...
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AC Characteristics of Programming Mode 10 Parameter PALE pulse width PMSEL setup to PALE rising edge Address setup to PALE, PROG, or PRD falling edge Address hold after PALE, ...
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PAW PALE t PMS PMSEL1,0 t PAS A8-A13 Port 2 Port 0 PROG Note: PRD must be high during a programming read cycle Figure 28 Programming Code Byte - Write Cycle Timing Data Sheet PAH A0-A7 ...
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PAW PALE t PMS PMSEL1,0 t Port 2 Port 0 PRD Note: PROG must be high during a programming read cycle Figure 29 Verify Code Byte - Read Cycle Timing Data Sheet PAS PAH A8-A13 t ...
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PMSEL1,0 Port 0 t PMS PROG PRD Note : PALE should be low during a lock bit read / write cycle Figure 30 Lock Bit Access Timing PMSEL1,0 Port 2 Port 0 PRD Note : PROG must be high during ...
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ROM/OTP Verification Characteristics for C504-2R / C504-2E ROM Verification Mode 1 (C504-2R only) Parameter Address to valid data P1.0 - P1.7 P2.0 - P2.5 Port 0 Address: P1 P2 ...
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ROM/OTP Verification Mode 2 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency t ALE Port 0 t P3.5 Figure 33 ROM Verification Mode 2 Data Sheet Symbol ...
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Inputs during testing are driven at Timing measurements are made at Figure 34 AC Testing: Input, Output Waveforms V Load V Load V Load For timing purposes a port pin is no longer ...
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Package Information P-MQFP-44 (SMD) (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet 66 C504 Dimensions in mm 2000-05 ...
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