sak-xc2766x-96f66l-ac Infineon Technologies Corporation, sak-xc2766x-96f66l-ac Datasheet
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XC2766X ...
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Edition 2008-03 Published by Infineon Technologies AG 81726 München, Germany © Infineon Technologies AG 2008. All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). ...
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XC2766X ...
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Preliminary XC2766X Revision History: V2.0, 2008-03 Previous Version(s): V0.1, 2007-09, Preliminary Page Subjects (major changes since last revision) 70ff Specification of pull devices improved 75ff Additional power consumption values incorporated 79 ADC errors added 82f Several system parameters specified 84f ...
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Preliminary 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Preliminary 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family 1 Summary of Features For a quick overview and easy reference, the features of the XC2766X are summarized here. • High-performance CPU with five-stage pipeline – instruction cycle at ...
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Preliminary – Four serial interface channels to be used as UART, LIN, high-speed synchronous channel (SPI/QSPI), IIC bus interface (10-bit addressing, 400 kbit/s), IIS interface – On-chip MultiCAN interface (Rev. 2.0B active) with 64 message objects (Full CAN/Basic CAN) 2 ...
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... Preliminary Table 1 XC2766X Derivative Synopsis 1) Derivative Temp. Range SAK-XC2766X- -40 °C to 125 °C 96F66L66 SAF-XC2766X- -40 ° °C 96F66L66 1) This Data Sheet is valid for devices starting with and including design step AB. 2) Specific inormation about the on-chip Flash memory in 3) All derivatives additionally provide 1 Kbyte SBRAM, 2 Kbytes DPRAM, and 16 Kbytes DSRAM. ...
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Preliminary 2 General Device Information The XC2766X derivatives XC2000 Family of full-feature single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They combine high CPU performance ...
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Preliminary 2.1 Pin Configuration and Definition The pins of the XC2766X are described in detail in functions. For further explanations please refer to the footnotes at the end of the table. Figure 2 summarizes all pins, showing their locations on ...
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Preliminary Notes to Pin Definitions 1. Ctrl.: The output signal for a port pin is selected by bitfield PC in the associated register Px_IOCRy. Output O0 is selected by setting the respective bitfield PC to 1x00 , output O1 is ...
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Preliminary Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B EMUX1 O1 U0C1_DOUT O2 U0C0_DOUT O3 CCU62_ I CCPOS1A TMS_C I U0C1_DX0F St/B EXTCLK O1 CCU62_ I ...
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Preliminary Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/A EMUX1 O1 T3OUT O2 U1C1_DOUT O3 ADCx_ I REQTRyC 13 P6 St/A EMUX2 O1 T6OUT O2 U1C1_ O3 SCLKOUT U1C1_DX1C ...
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Preliminary Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 24 P5.3 I ADC0_CH3 I T3IN I 28 P5.4 I ADC0_CH4 I CCU63_ I T12HRB T3EUD I TMS_A I 29 P5.5 I ADC0_CH5 I CCU60_ I T12HRB 30 P5.8 ...
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Preliminary Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 35 P5.15 I ADC0_CH15 I 36 P2. St/B U0C0_ O1 SELO4 U0C1_ O2 SELO3 READY I 37 P2. St/B U0C0_ O1 SELO2 U0C1_ ...
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Preliminary Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B TxDC1 O1 CCU63_ St/B CC62 AD15 St/B ESR2_5 I EX1AINA St/B ...
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Preliminary Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U0C0_ O1 SCLKOUT TxDC0 O2 CC2_18 St/B A18 OH U0C0_DX1D St/B CC2_26 O3 / ...
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Preliminary Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U0C1_ O1 SELO0 U0C0_ O2 SELO1 CC2_20 St/B A20 OH U0C1_DX2C I RxDC1C St/B ...
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Preliminary Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U1C0_ O1 SCLKOUT TxDC0 O2 CCU61_ St/B CC62 A2 OH U1C0_DX1B I 59 P10 St/B U0C1_DOUT O1 ...
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Preliminary Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U1C0_ O1 SELO0 U1C1_ O2 SELO1 CCU61_ O3 COUT60 A3 OH U1C0_DX2A I RxDC0B I 62 P10 St/B U0C0_ O1 ...
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Preliminary Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 66 P2. St/B U0C1_DOUT O1 U0C0_ O2 SELO3 CC2_23 St/B A23 OH U0C1_DX0E I CAPIN I 67 P10 St/B CCU60_ ...
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Preliminary Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 70 P10 St/B U0C1_ O1 SCLKOUT CCU60_ O2 COUT62 AD5 St/B U0C1_DX1B St/B U1C1_DOUT O1 TxDC1 O2 ...
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Preliminary Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 73 P10 St/B U0C1_DOUT O1 CCU60_ O2 COUT63 AD7 St/B U0C1_DX0B I CCU60_ I CCPOS0A 74 P0 St/B U1C1_DOUT O1 ...
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Preliminary Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 79 P10 St/B U0C0_ O1 MCLKOUT U0C1_ O2 SELO0 AD8 St/B CCU60_ I CCPOS1A U0C0_DX1C I BRKIN_B I 80 P10 ...
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Preliminary Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 82 P10. St/B U0C0_ O1 SELO0 CCU60_ O2 COUT63 AD10 St/B U0C0_DX2C I TDI_B I U0C1_DX1A I 83 P10. St/B ...
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Preliminary Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 85 P10. St/B U1C0_DOUT O1 TDO_B O3 AD12 St/B U1C0_DX0C I U1C0_DX1E I 86 P10. St/B U1C0_DOUT O1 U1C0_ O3 ...
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Preliminary Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 89 P10. St/B U1C0_ O1 SELO1 U0C1_DOUT ESR2_2 I U0C1_DX0C St/B CCU62_ O1 COUT61 U1C1_ O2 SELO4 ...
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Preliminary Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B CCU62_ St/B CC61 U1C1_ O2 SELO2 U2C0_DOUT O3 A14 OH U2C0_DX0D St/B CCU62_ O1 ...
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Preliminary Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 98 ESR1 St/B U1C0_DX0F I U1C0_DX2C I U1C1_DX0C I U1C1_DX2B I U2C1_DX2C I EX0AINB I 99 ESR0 St/B U1C0_DX0E I U1C0_DX2B I V ...
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Preliminary Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl DDPB 25, 27, 50, 52, 75, 77, 100 26, 51 generate the reference clock output for bus timing measurement, ...
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Preliminary 3 Functional Description The architecture of the XC2766X combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a well-balanced design. On-chip memory blocks allow the design of compact systems-on-silicon with maximum performance suited for ...
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Preliminary 3.1 Memory Subsystem and Organization The memory space of the XC2766X is configured in the von Neumann architecture. In this architecture all internal and external resources, including code memory, data memory, registers and I/O ports, are organized in the ...
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Preliminary This common memory space consists of 16 Mbytes organized as 256 segments of 64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory space can be accessed bytewise or wordwise. Portions of the on-chip DPRAM ...
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Preliminary 1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are word-wide registers which are used to control and monitor functions of the different on-chip ...
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Preliminary 3.2 External Bus Controller All external memory access operations are performed by a special on-chip External Bus Controller (EBC). The EBC also controls access to resources connected to the on-chip LXBus (MultiCAN and the USIC modules). The LXBus is ...
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Preliminary 3.3 Central Processing Unit (CPU) The core of the CPU consists of a 5-stage execution pipeline with a 2-stage instruction- fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply and accumulate unit (MAC), a register-file providing ...
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Preliminary With this hardware most XC2766X instructions can be executed in a single machine cycle with a 66 MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle, no matter how ...
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Preliminary 3.4 Interrupt System With a minimum interrupt response time of 7/11 program execution), the XC2766X can react quickly to the occurrence of non- deterministic events. The architecture of the XC2766X supports several mechanisms for fast and flexible response to ...
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Preliminary Table 6 XC2766X Interrupt Nodes Source of Interrupt or PEC Service Request CAPCOM Register 16, or ERU Request 0 CAPCOM Register 17, or ERU Request 1 CAPCOM Register 18, or ERU Request 2 CAPCOM Register 19, or ERU Request ...
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Preliminary Table 6 XC2766X Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request GPT2 CAPREL Register CAPCOM Timer 7 CAPCOM Timer 8 A/D Converter Request 0 A/D Converter Request 1 A/D Converter Request 2 A/D Converter Request 3 A/D ...
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Preliminary Table 6 XC2766X Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request CAN Request 3 CAN Request 4 CAN Request 5 CAN Request 6 CAN Request 7 CAN Request 8 CAN Request 9 CAN Request 10 CAN Request ...
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Preliminary Table 6 XC2766X Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node SCU Request 1 SCU Request 0 ...
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Preliminary The XC2766X includes an excellent mechanism to identify and process exceptions or error conditions that arise during run-time, the so-called ‘Hardware Traps’. A hardware trap causes an immediate non-maskable system reaction similar to a standard interrupt service (branching to ...
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Preliminary 3.5 On-Chip Debug Support (OCDS) The On-Chip Debug Support system built into the XC2766X provides a broad range of debug and emulation features. User software running on the XC2766X can be debugged within the target system environment. The OCDS ...
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Preliminary 3.6 Capture/Compare Unit (CAPCOM2) The CAPCOM2 unit supports generation and control of timing sequences channels with a maximum resolution of one system clock cycle (eight cycles in staggered mode). The CAPCOM2 unit is typically used ...
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Preliminary When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (‘captured’) into the capture/compare register in response to an external event at the port pin associated with this register. ...
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Preliminary T7IN T6OUF CCxIO CCxIO CCxIO T6OUF CAPCOM2 provides channels … 31. (see signals CCxIO and CCxIRQ) Figure 5 CAPCOM2 Unit Block Diagram Data Sheet Reload Reg. T7REL T7 Input Timer ...
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Preliminary 3.7 Capture/Compare Units CCU6x The XC2766X features four CCU6 units (CCU60, CCU61, CCU62, CCU63). The CCU6 is a high-resolution capture and compare unit with application-specific modes. It provides inputs to start the timers synchronously, an important feature in devices ...
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Preliminary f SYS TxHR T12 Interrupts st art T13 Figure 6 CCU6 Block Diagram Timer T12 can work in capture and/or compare mode for its three channels. The modes can also be combined. Timer T13 can work in compare mode ...
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Preliminary 3.8 General Purpose Timer (GPT12E) Unit The GPT12E unit is a very flexible multifunctional timer/counter structure which can be used for many different timing tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, ...
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Preliminary T3CON.BPS1 GPT T2IN T2 Mode Control T2EUD T3 T3IN Mode Control T3EUD T4IN T4 Mode Control T4EUD Figure 7 Block Diagram of GPT1 Data Sheet XC2000 Family Derivatives Basic Clock Aux. Timer T2 U/D Reload ...
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Preliminary With its maximum resolution of 2 system clock cycles, the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock ...
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Preliminary T6CON.BPS2 GPT T5IN Mode T5EUD Control CAPIN CAPREL Mode Control T3IN/ T3EUD Mode T6IN Control T6EUD Figure 8 Block Diagram of GPT2 Data Sheet Basic Clock GPT2 Timer T5 T5 U/D Clear Capture GPT2 CAPREL ...
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Preliminary 3.9 Real Time Clock The Real Time Clock (RTC) module of the XC2766X can be clocked with a clock signal selected from internal sources or external sources (pins). The RTC basically consists of a chain of divider blocks: • ...
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Preliminary The RTC module can be used for different purposes: • System clock to determine the current time and date • Cyclic time-based interrupt, to provide a system time tick independent of CPU frequency and other resources • 48-bit timer ...
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Preliminary 3.10 A/D Converters For analog signal measurement two 10-bit A/D converters (ADC0, ADC1) with multiplexed input channels and a sample and hold circuit have been integrated on-chip. They use the successive approximation method. The ...
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Preliminary 3.11 Universal Serial Interface Channel Modules (USIC) The XC2766X includes two USIC modules (USIC0, USIC1), each providing two serial communication channels. The Universal Serial Interface Channel (USIC) module is based on a generic data shift and data storage structure ...
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Preliminary Target Protocols Each USIC channel can receive and transmit data frames with a selectable data word width from bits in each of the following protocols: • UART (asynchronous serial channel) – maximum baud rate: – data ...
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Preliminary 3.12 MultiCAN Module The MultiCAN module contains two independently operating CAN nodes with Full-CAN functionality which are able to exchange Data and Remote Frames using a gateway function. Transmission and reception of CAN frames is handled in accordance with ...
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Preliminary MultiCAN Features • CAN functionality conforming to CAN specification V2.0 B active for each CAN node (compliant to ISO 11898) • Two independent CAN nodes • 64 independent message objects (shared by the CAN nodes) • Dedicated control registers ...
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Preliminary 3.13 Watchdog Timer The Watchdog Timer is one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after an application reset of the ...
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Preliminary 3.15 Parallel Ports The XC2766X provides I/O lines which are organized into 7 input/output ports and 2 input ports. All port lines are bit-addressable, and all input/output lines can be individually (bit-wise) configured via port control ...
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Preliminary Table 9 Summary of the XC2766X’s Parallel Ports (cont’d) Port Width Alternate Functions Port 6 4 ADC control lines, Serial interface lines of USIC1, Timer control signals, OCDS control Port 7 5 ADC control lines, Serial interface lines of ...
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Preliminary 3.16 Instruction Set Summary Table 10 lists the instructions of the XC2766X. The addressing modes that can be used with a specific instruction, the function of the instructions, parameters for conditional execution of instructions, and the opcodes for each ...
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Preliminary Table 10 Instruction Set Summary (cont’d) Mnemonic Description ROL/ROR Rotate left/right direct word GPR ASHR Arithmetic (sign bit) shift right direct word GPR MOV(B) Move word (byte) data MOVBS/Z Move byte operand to word op. with sign/zero extension JMPA/I/R ...
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Preliminary Table 10 Instruction Set Summary (cont’d) Mnemonic Description NOP Null operation CoMUL/CoMAC Multiply (and accumulate) CoADD/CoSUB Add/Subtract Co(A)SHR (Arithmetic) Shift right CoSHL Shift left CoLOAD/STORE Load accumulator/Store MAC register CoCMP Compare CoMAX/MIN Maximum/Minimum CoABS/CoRND Absolute value/Round accumulator CoMOV Data ...
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Preliminary 4 Electrical Parameters The operating range for the XC2766X is defined by its electrical parameters. For proper operation the specified limits must be respected during system design. Note: Typical parameter values refer to room temperature and nominal supply voltage, ...
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Preliminary Operating Conditions The following operating conditions must not be exceeded to ensure correct operation of the XC2766X. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 12 Operating Condition Parameters Parameter Digital ...
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Preliminary Table 12 Operating Condition Parameters (cont’d) Parameter External Pin Load Capacitance Voltage Regulator Buffer Capacitance for DMP_M Voltage Regulator Buffer Capacitance for DMP_1 Ambient temperature 1) If both core power domains are clocked, the difference between the power supply ...
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Preliminary Parameter Interpretation The parameters listed in the following include both the characteristics of the XC2766X and its demands on the system. To aid in correctly interpreting the parameters when evaluating them for a design, they are marked accordingly in ...
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Preliminary 4.2 DC Parameters These parameters are static or average values that may be exceeded during switching transitions (e.g. output current). The XC2766X can operate within a wide supply voltage range from 3 5.5 V. However, during operation ...
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Preliminary Pullup/Pulldown Device Behavior Most pins of the XC2766X feature pullup or pulldown devices. For some special pins these are fixed; for the port pins they can be selected by the application. The specified current values indicate how to load ...
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Preliminary 4.2.1 DC Parameters for Upper Voltage Area These parameters apply to the upper IO voltage range, 4.5 V ≤ Table 14 DC Characteristics for Upper Voltage Range (Operating Conditions apply) Parameter Input low voltage (all except XTAL1) Input low ...
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Preliminary Table 14 DC Characteristics for Upper Voltage Range (cont’d) (Operating Conditions apply) Parameter XTAL1 input current 10) Pin capacitance (digital inputs/outputs) 1) Keeping signal levels within the limits specified in this table ensures operation without overload conditions. For signal ...
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Preliminary 4.2.2 DC Parameters for Lower Voltage Area These parameters apply to the lower IO voltage range, 3.0 V ≤ Table 15 DC Characteristics for Lower Voltage Range (Operating Conditions apply) Parameter Input low voltage (all except XTAL1) Input low ...
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Preliminary Table 15 DC Characteristics for Lower Voltage Range (cont’d) (Operating Conditions apply) Parameter XTAL1 input current 10) Pin capacitance (digital inputs/outputs) 1) Keeping signal levels within the limits specified in this table ensures operation without overload conditions. For signal ...
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Preliminary 4.2.3 Power Consumption The power consumed by the XC2766X depends on several factors such as supply voltage, operating frequency, active circuits, and operating temperature. The power consumption specified here consists of two components: • The switching current I • ...
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Preliminary Table 16 Switching Power Consumption XC2766X (Operating Conditions apply) Parameter Power supply current (active) with all peripherals active and EVVRs on Power supply current in stopover mode, EVVRs on 1) The pad supply voltage pins ( by the pin ...
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Preliminary I [mA] S 100 Figure 13 Supply Current in Active Mode as a Function of Frequency Data Sheet XC2000 Family Derivatives XC2766X Electrical Parameters I SACTmax ...
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Preliminary Table 17 Leakage Power Consumption XC2766X (Operating Conditions apply) Parameter 2) Leakage supply current 3) -α : 600,000 × e Formula ; α = 5000 / (273 + B× Typ 1.0, Max ...
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Preliminary 4.3 Analog/Digital Converter Parameters These parameters describe the conditions for optimum ADC performance. Table 18 A/D Converter Characteristics (Operating Conditions apply) Parameter Analog reference supply Analog reference ground Analog input voltage range Analog clock frequency Conversion time for 10-bit ...
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Preliminary Table 18 A/D Converter Characteristics (cont’d) (Operating Conditions apply) Parameter Switched capacitance of the reference input Resistance of the reference input path TUE is tested at = AREFx DDPA voltage range. The specified TUE is valid ...
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Preliminary Sample time and conversion time of the XC2766X’s A/D converters are programmable. The timing above can be calculated using f The limit values for must not be exceeded when selecting the prescaler value. ADCI Table 19 A/D Converter Computation ...
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Preliminary 4.4 System Parameters The following parameters specify several aspects which are important when integrating the XC2766X into an application system. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 20 Various System ...
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Preliminary Table 21 Coding of Bitfields LEVxV in Register SWDCON0 Code Default Voltage Level 0000 2 0001 3 0010 3 0011 3 0100 3 0101 3 0110 3.6 ...
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Preliminary 4.5 Flash Memory Parameters The data retention time of the XC2766X’s Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed. Note: ...
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Preliminary Table 24 Flash Access Waitstates Required Waitstates 4 WS (WSFLASH = 100 (WSFLASH = 011 (WSFLASH = 010 (WSFLASH = 001 (WSFLASH = 000 B Note: The ...
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Preliminary 4.6 AC Parameters These parameters describe the dynamic behavior of the XC2766X. 4.6.1 Testing Waveforms These values are used for characterization and production testing (except pin XTAL1). Output delay Hold time 0.8 V DDP 0.7 V DDP 0.3 V ...
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Preliminary 4.6.2 Definition of Internal Timing The internal operation of the XC2766X is controlled by the internal system clock Because the system clock signal external sources using different mechanisms, the duration of the system clock periods (TCSs) and their variation ...
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Preliminary Direct Drive When direct drive operation is selected (SYSCON0.CLKSEL = 11 derived directly from the input clock signal CLKIN1 SYS IN f The frequency of is the same as the frequency of SYS f times ...
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Preliminary The timing in the AC Characteristics refers to TCSs. Timing must be calculated using the minimum TCS possible under the given circumstances. The actual minimum value for TCS depends on the jitter of the PLL. Because the PLL is ...
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Preliminary D Acc. jitter T ns ±9 ±8 ±7 ±6 ±5 ±4 ±3 ±2 ± Figure 19 Approximated Accumulated PLL Jitter Note: The specified PLL jitter values are valid if the capacitive load per pin does not ...
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Preliminary Wakeup Clock When wakeup operation is selected (SYSCON0.CLKSEL = 00 derived from the low-frequency wakeup clock source SYS WU In this mode, a basic functionality can be maintained without requiring an external clock source and ...
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Preliminary 4.6.3 External Clock Drive These parameters specify the external clock for the XC2766X. The clock signal can be supplied either to pin P2 pin XTAL1. Table 26 External Clock Drive Characteristics (Operating Conditions apply) Parameter Oscillator period ...
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Preliminary 4.6.4 External Bus Timing The following parameters specify the behavior of the XC2766X bus interface. Table 27 CLKOUT Reference Signal Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time 1) The CLKOUT ...
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Preliminary Variable Memory Cycles External bus cycles of the XC2766X are executed in five consecutive cycle phases (AB F). The duration of each cycle phase is programmable (via the TCONCSx registers) to adapt the external bus cycles ...
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Preliminary Table 29 External Bus Cycle Timing for Upper Voltage Range (Operating Conditions apply) Parameter Output valid delay for: RD, WR(L/H) Output valid delay for: BHE, ALE Output valid delay for: A23 … A16, A15 … A0 (on P0/P1) Output ...
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Preliminary Table 30 External Bus Cycle Timing for Lower Voltage Range (Operating Conditions apply) Parameter Output valid delay for: RD, WR(L/H) Output valid delay for: BHE, ALE Output valid delay for: A23 … A16, A15 … A0 (on P0/P1) Output ...
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Preliminary tp CLKOUT t 11 ALE A23-A16, BHE, CSx RD WR(L/H) t AD15-AD0 (read) t AD15-AD0 (write) Figure 22 Multiplexed Bus Cycle Data Sheet High Address t 10 ...
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Preliminary tp AB CLKOUT t 11 ALE A23-A0, BHE, CSx RD WR(L/H) D15-D0 (read) D15-D0 (write) Figure 23 Demultiplexed Bus Cycle Data Sheet Address ...
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Preliminary Bus Cycle Control with the READY Input The duration of an external bus cycle can be controlled by the external circuit using the READY input signal. The polarity of this input signal can be selected. Synchronous READY permits the ...
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Preliminary CLKOUT RD, WR D15-D0 (read) D15-D0 (write) READY Synchronous READY Asynchron. Figure 24 READY Timing Note: If the READY input is sampled inactive at the indicated sampling point (“Not Rdy”) a READY-controlled waitstate is inserted (tpRDY), sampling the READY ...
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Preliminary 4.6.5 Synchronous Serial Interface Timing The following parameters are applicable for a USIC channel operated in SSC mode. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 31 SSC Master/Slave Mode Timing ...
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Preliminary Table 32 SSC Master/Slave Mode Timing for Lower Voltage Range (Operating Conditions apply), Parameter Master Mode Timing Slave select output SELO active to first SCLKOUT transmit edge Slave select output SELO inactive after last SCLKOUT receive edge Transmit data ...
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Preliminary Master Mode Timing Select Output Inactive SELOx Clock Output SCLKOUT Data Output DOUT Data Input DX0 Slave Mode Timing Select Input Inactive DX2 Clock Input DX1 Data Input DX0 Data Output DOUT Transmit Edge: with this clock edge , ...
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Preliminary 4.6.6 JTAG Interface Timing The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000. Note: These parameters are not subject to production test but verified by design and/or characterization. ...
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Preliminary V 0.5 DDP t 2 Figure 26 Test Clock Timing (TCK) TCK TMS TDI t 9 TDO Figure 27 JTAG Timing Data Sheet 105 XC2766X XC2000 Family ...
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Preliminary 5 Package and Reliability In addition to the electrical parameters, the following specifcations ensure proper integration of the XC2766X into the target system. 5.1 Packaging These parameters specify the packaging rather than the silicon. Table 34 Package Parameters (PG-LQFP-100) ...
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Preliminary Package Outlines Figure 28 PG-LQFP-100 (Plastic Green Thin Quad Flat Package) All dimensions in mm. You can find complete information about Infineon packages, packing and marking in our Infineon Internet Page “Packages”: Data Sheet XC2000 Family Derivatives http://www.infineon.com/packages 107 ...
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Preliminary 5.2 Thermal Considerations When operating the XC2766X in a system, the total heat generated in the chip must be dissipated to the ambient environment to prevent overheating and the resulting thermal damage. The maximum heat that can be dissipated ...
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