CLC446 National Semiconductor, CLC446 Datasheet - Page 6

• Manufacturer Part Number: CLC446
• Description: 400MHz/ 50mW Current-Feedback Op Amp
• Manufacturer: National Semiconductor

where
DC Design (DC offsets)
The DC offset model shown in Figure 6 is used to
calculate the output offset voltage. The equation for out-
put offset voltage is:
The current offset terms, I
other . The specifications are stated in terms of magni-
tude only. Therefore, the terms V
either polarity. Matching the equivalent resistance seen
at both input pins does not reduce the output
offset voltage.
DC Design (output loading)
R
load seen by the output in Figure 6 is:
R
put current can produce the required output voltage
swing.
AC Design (small signal bandwidth)
The CLC446 current-feedback amplifier bandwidth is
a function of the feedback resistor (R
voltage gain (A
proportional to
width is cut in half. Other AC specifications will also be
degraded. Decreasing R
increases peaking, and for very small values of R
lation will occur .
AC Design (minimum slew rate)
Slew rate influences the bandwidth of large signal
sinusoids. To determine an approximate value of slew
rate necessary to support a large sinusoid, use the
following equation:
where V
http://www.national.com
L
L(eq)
, R
f
, and R
needs to be large enough so that the minimum out-
V
R
R
o
peak
L(eq)
L(eq)
R
eq1
is the peak output sinusoidal voltage.
s
g
V
= R
= R
Figure 6: DC Offset Model
1
2
os
load the op amp output. The equivalent
R
SR
1
j
V
f
L
L
R
). The bandwidth is approximately
R R
. As a rule, if R
|| (R
|| R
I
R
g
1
BN
I
I
eq2
BN
BI
5
V
C
+
f
-
os
, inverting gain
f
•
R
2
2
+ R
f
f
eq1
•
BN
from the recommended value
CLC446
+
C
-
V
eq2
1
peak
and I
), non-inverting gain
1
os
R
R
, I
f
BI
R
f
eq2
BN
,
doubles, the band-
f
do not track each
, and I
f
), not of the DC
R
I
V
BI
L
BI
o
R
can have
f
f
oscil-
6
The slew rate of the CLC446 in inverting gains is always
higher than in non-inverting gains.
AC Design (linear phase/constant group delay)
The recommended value of R
peaking and a reasonably linear phase response.
To improve phase linearity when |A
approximately 50% over its recommended value. Some
adjustment of R
earity for your application. See the AC Design (small
signal bandwidth) sub-section for other effects of
changing R
Propagation delay is approximately equal to group delay.
Group delay is related to phase by this equation:
where (f) is the phase in degrees. Linear phase implies
constant group delay. The technique for achieving linear
phase also produces a constant group delay.
AC Design (peaking)
Peaking is sometimes observed with the recommended
R
then investigate the possible causes and remedies
listed below.
For non-inverting and transimpedance gain configurations:
For inverting gain configurations:
Capacitive Loads
Capacitive loads, such as found in A/D converters,
require a series resistor (R
improve settling performance.
R
Characteristics section provides the information for
selecting this resistor.
f
s
. If a small increase in R
Capacitance across R
A capacitive load
Long traces and/or lead lengths between R
the CLC446
Extra capacitance between the inverting pin
and ground (C
Inadequate ground plane at the non-inverting pin
and/or long traces between non-inverting pin
and ground
vs. C
Do not place a capacitor across R
Use a resistor with low parasitic
capacitance for R
Use a series resistor between the output and
a capacitive load (see the Recommended
R
Keep these traces as short as possible
See the Printed Circuit Board Layout sub-
section below for suggestions on reducing C
Increase R
reducing C
Place a 50 to 200
inverting pin and ground (see R
s
vs. C
f
.
L
gd
plot in the Typical Performance
f
L
g
)
may be needed to achieve phase lin-
plot)
f
f
g
if peaking is still observed after
360
f
f
1
f
resistor between the non-
does not solve the problem,
d f
df
s
) in the output to
The Recommended
f
v
produces minimal
| < 5, increase R
t
in Figure 2)
f
f
f
f
and
g
f