M58LW064 ST Microelectronics, M58LW064 Datasheet
M58LW064
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M58LW064 Summary of contents
Page 1
... Double-Word basis using a 2.7V to 3.6V supply for the circuit and a supply down to 1.8V for the Input and Output buffers. The M58LW064A is organised bit. The M58LW064B has bit bit organisation selectable by the Word Organisation WORD input. Both devices are internally configured as 64 blocks of 1 Mbit each ...
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... Status and the Burst Configuration Registers are cleared. A recovery time is required when the RP input goes High. The device is offered in various package versions, TSOP56 ( mm), TSOP86 Type II (11.76 x 22.22 mm) and LBGA54 1mm ball pitch for the M58LW064A and PQFP80 for the M58LW064B. ...
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... V DD A15 A14 A13 A12 M58LW064A A11 A10 AI03224 M58LW064A, M58LW064B Figure 3. TSOP86 Type II Connections A11 G A10 RB A9 DQ15 A8 DQ7 V SS DQ14 V SS DQ6 DQ13 A5 DQ5 A4 DQ12 A3 ...
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... M58LW064A, M58LW064B Figure 4. LBGA Connections for M58LW064A (Top view through package DQ8 DQ1 F K DQ0 4/ A13 A14 A10 A12 A15 A11 RP DQ9 DQ3 DQ4 DQ10 DQ11 ...
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... Figure 5. PQFP Connections DQ16 DQ24 12 DQ17 DQ25 DQ18 DQ26 DQ19 DQ27 DQ0 DQ8 M58LW064A, M58LW064B 73 M58LW064B 53 32 AI03546 A19 A20 A21 R A22 WORD DQ31 DQ23 DQ30 DQ22 DQ29 DQ21 DQ28 DQ20 DQ15 ...
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... M58LW064A, M58LW064B Table 2. Absolute Maximum Ratings Symbol T Ambient Operating Temperature A T Temperature Under Bias BIAS T Storage Temperature STG V Input or Output Voltage Supply Voltage DD DDQ V RP Hardware Block Unlock Voltage HH Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device ...
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... A Word Organisation WORD input selects the x16 or x32 data width for the M58LW064B. For the x16 only organisation of the M58LW064A or the x16 organisation of the M58LW064B the address lines are A1-A22 and the Data Input/Output is on DQ0- DQ15 ...
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... M58LW064A, M58LW064B BUS OPERATIONS The following operations can be performed using the appropriate bus configuration: Asynchronous – Read Array – Read Electronic Signature – Read Block Protection – Read Status Register – Read Query – Write – Output Disable – Standby – Reset/Power-down Synchronous – ...
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... Table 6. M58LW064A CFI Block Protection Status Query Operation Block Status Protected IL IL Unprotected Note Dont’Care Table 7. M58LW064B CFI Block Protection Status Query Operation Block Status Protected IL IL Unprotected Note Dont’Care ...
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... See Figure 1 and Table 1. Address Inputs (A1-A22 used to select between the high and low Word in the x16 config- uration of the M58LW064A or B. For the M58LW064B A1 is not used in the x32 mode. When Chip Enable the address bus is IL ...
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... R going to V Word Organisation (WORD). The Word Organi- sation WORD input is present only on the M58LW064B and selects x16 or x32 organisation. The WORD input selects the data width as Word wide (x16) or Double-Word wide (x32). When WORD ...
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... M58LW064A, M58LW064B DEVICE OPERATIONS See Tables and 10. Address Latch. An address is latched on the ris- ing edge of the Latch Enable L input for Asynchro- nous Latch Enable Controlled Asynchrouns Latch Enable Controlled Write, the address is latched on the rising edge of Chip En- able E, Write Enable W or Latch Enable L, which- ever occurs first ...
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... Signature is output by giving the RSIG Instruction. The manufacturer code is output when all the Ad- dress inputs are Low. The device code is output when A1 (M58LW064A (M58LW064B) in- put is High, the other pins A3-A22 must be Low. The codes are output on DQ0-DQ7. A return to Read mode is achieved by writing the Read Array instruction ...
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... M58LW064A, M58LW064B M8 Valid Data Ready R Signal Configuration. The Valid Data Ready R output signal indicates when valid data is on the data outputs synchro- nous with the valid burst clock egde. It can be as- serted by the device synchronously with the valid clock edge or one clock cycle before. ...
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... Table 8. Burst Type Definition (x16 mode) Starting Address (binary) Burst Length A3-A2-A1 0-0-0 2 0-0-1 0-0-0 0-0-1 4 0-1-0 0-1-1 0-0-0 0-0-1 0-1-0 0-1-1 8 1-0-0 1-0-1 1-1-0 1-1-1 Table 9. Burst Type Definition (x32 mode) Starting Address (binary) Burst Length A2-A1 0-0 2 0-1 0-0 0-1 4 1-0 1-1 M58LW064A, M58LW064B Sequential Interleaved (decimal) (decimal) 0-1 0-1 1-0 1-0 0-1-2-3 0-1-2-3 1-2-3-0 1-0-3-2 2-3-0-1 2-3-0-1 3-0-1-2 3-2-1-0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Sequential Interleaved (decimal) (decimal) 0-1 0-1 1-0 1-0 0-1-2-3 0-1-2-3 1-2-3-0 1-0-3-2 2-3-0-1 2-3-0-1 3-0-1-2 3-2-1-0 15/53 ...
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... M58LW064A, M58LW064B Table 10. Burst Configuration Register BCR mode bit Description M15 Read Select (4) M14-M11 X-Latency (4) M9 Y-Latency M8 Valid Data Ready M7 Burst Type M6 Valid Clock Edge M3 Asynchronous (2) M2-M0 Burst Length Note: 1. The BCR defines both the read mode and the burst configuration. 2. Synchronous burst length is defined as Word or Double-Word, the data bus width depends only on the WORD input. ...
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... Sequential Interleaved Sequential Burst length: Burst length: Burst length: 1,2,4,8 1,2,4,8 8.1.1.1 8.1.1.1 8.1.1.1 12.1.1.1 12.1.1.1 12.1.1.1 t.b.a. t.b.a. 16.2.2.2 16.2.2.2 16.2.2.2 Note: 1. The burst length not available in the x32 organisation. x16 x32 organisation organisation Interleaved V DD Burst length: Continuo us Burst 1,2,4 1,2,4 8.1.1.1 7.1.1.1 12.1.1.1 10.1.1.1 t.b.a. t.b.a. t.b.a. 16.2.2.2 14.2.2.2 M58LW064A, M58LW064B x32 organisation Clock Frequency = 2.7 to 3.6V 7.1.1.1 33 MHz 10.1.1.1 50 MHz t.b.a. 60 MHz 14.2.2.2 66 MHz 17/53 ...
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... Manu- facturer Code, the Device Code or the Block Pro- tection Status. The Manufacturer Code is output when all the address inputs are at VIL. The Device Code is output when A1 (for the M58LW064A (for the M58LW064B with all other IH address inputs at V ...
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... Write Unprotect dis-activated by Chip Enable E High and then re- activated by Chip Enable E and Output Enable G Low, during an Erase or Program operation. The content of Status Register may also be read at the completion of an Erase/Program and/or Suspend M58LW064A, M58LW064B 1st Cycle 2nd Cycle Address Data Op. Address ...
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... M58LW064A, M58LW064B Table 13. Status Register Definition Mnemonic DQ Function P/ECS DQ7 P/E.C. Status ESS DQ6 Erase Suspend Status ES DQ5 Erase/Block Unprotect Status Write to Buffer and Program/Block PS DQ4 (7) Protect Status DQ3 Not used PSS DQ2 Program Suspend Status Erase/Write to Buffer and Program in a EPPB ...
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... In the third step, a sequence of N+1 write cycles loads the addresses and data to the write buffer (see boundary constraints below). The addresses M58LW064A, M58LW064B must lie between the starting address and the starting address + (N+1). The array must be programmed in 4 Word or 2 Double-Word blocks, which must be aligned with starting address ( for x32 organisation) ...
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... M58LW064A, M58LW064B Block Unprotect Instruction (BU). The Unprotect Instruction BU uses a two-cycle write sequence. All the Block Protect bits are simulta- neously erased. The Block Protect bit register is erased by giving the command 60h and then the Confirm command D0h, at any address location. The sequence is aborted if the Confirm command is not given and the device will output the Status Register Data with DQ4 and DQ5 set to ’ ...
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... The device is reset if the Reset/Power-down RP input is pulled to V for longer than tPLPH. If the IL device was in a Read mode then it will recover M58LW064A, M58LW064B from reset after a time give valid data PHQV output. If the device was executing an Erase or Program operation, with the P/E.C. active, the op- eration will abort in a time of t maximum ...
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... Note: 1. The x8 or Byte Address mode is not available the x16 organization, the value of the address location of the CFI Query is independent of A1 pad (M58LW064B). 3. Query Data are always presented on the lowest order data outputs (DQ7-DQ0) only. Others data (DQ31-DQ8) are set to ’0’. ...
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... Note: 1. For M58LW064B Don’t Care. M58LW064A, M58LW064B Instruction V Min, 2. max, 3. min – Not Available PP V max – Not Available Word, DWord prog. typical time-out ...
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... Table 18. Block Status Register (see also, Table 6 and 7 in the datasheet) Address Data (Hex) x32 organization A22-A2 bit0 (1) (BA+3)h bit1 bit7-2 Note specifies the block address location, i-e, A22-A17. 2. Not Supported. Table 19. Extended Query information M58LW064B - x32 M58LW064A - x16 Address Address Data (Hex) offset A22-A2 x32 organization (P)h 31h 50h ”P” (P+1)h 32h 52h ” ...
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... Output Capacitance OUT Figure 8. AC Testing Load Circuit 3ns 4ns DDQ V /2 DDQ DEVICE UNDER TEST V DDQ / includes JIG capacitance AI00610 Test Condition Typ OUT M58LW064A, M58LW064B 1.3V 1N914 3.3k OUT 30pF AI03229 Max Unit 27/53 ...
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... M58LW064A, M58LW064B Table 22. DC Characteristics ( – 2.7V to 3.6V Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Supply Current (Random Read Supply Current (Burst Read) CCB Supply Current (Standby) I CC1 Supply Current (Auto Low-Power) I Supply Current (Reset/Power-down) ...
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... after the falling edge of Chip Enable E without increasing t ELQV GLQV VALID tGLQX tGLQV tGHQX tGHQZ OUTPUT See also Page Read M58LW064A, M58LW064B Min Max Unit 150 ns 150 150 ...
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... M58LW064A, M58LW064B Table 24. Asynchronous Latch Enable Controlled Read and Page Read ( – 2.7V to 3.6V Symbol Parameter t Address Valid to Lacth Enable Low AVLL t Address Valid to Output Valid (Page Read) AVQV1 t Address Transition to Output Transition (Page Read) AXQX t Chip Enable High to Latch Enable Transition ...
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... See Asynchronous Random Read or Asynchronous Latch Enable Controlled Read A1 and/or A2 only may change in x16 organization, A2 only in x32 organization (1) Only for Latch Enable Controlled Read (2) M58LW064A, M58LW064B A1 and/or A2 (x16), A2 (x32) tLLQV1 tAVQV1 tAXQX OUTPUT OUTPUT + 1 Page Read Words in x16 organization - 2 Double-Words in x32 orognization ...
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... M58LW064A, M58LW064B Table 25. Synchronous Burst Read ( – 2.7V to 3.6V (2) Parameter Symbol t Address Valid to Latch Enable Low AVLL t Burst Address Advance High toValid Clock Edge BHKH t Burst Address Advance Low to Valid Clock Edge BLKH t Chip Enable Low to Latch Enable low ...
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... Figure 13. Synchronous Burst Read (8.1.1.1 example) X-Latency = 8 (M14-M11 = 0010), Y-Latency = 1 (M9 = 0), Burst Length = 1 (M2-M0 = 100), Burst Type = Any ( 1), Valid Clock Edge = Rising ( M58LW064A, M58LW064B 33/53 ...
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... M58LW064A, M58LW064B Figure 14. Synchronous Burst Read - Continuous - Valid Data Ready Output Valid Data Ready = Valid Low during valid clock edge ( (1) Output Valid output Not Valid output. ( open drain output with an internal pull up resistor of 1M (2) The internal timing of R follows DQ. An external resistor, typically 300k for a single memory on the R Bus, should be used to give a data valid set up time required to recognize valid data is evailable on the next valid clock edge ...
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... Valid clock edge ’9’ is valid and outputs Q0. (2) B goes low before valid clock edge ’10’ and output increments to Q1. (3) B goes high before valid clock edge ’12’ and output remains Q1 tBLKH tBHKH (3) M58LW064A, M58LW064B AI03697 35/53 ...
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... M58LW064A, M58LW064B Table 26. Asynchronous Write and Latch Enable Controlled Write ( – 2.7V to 3.6V Symbol Parameter t Address Valid to Latch Enable High AVLH t Address Valid to Write Enable High AVWH t Data Input Valid to Write Enable High DVWH t Chip Enable Low to Write Enable Low ...
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... Figure 17. Asynchronous Write M58LW064A, M58LW064B 37/53 ...
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... M58LW064A, M58LW064B Figure 18. Asynchronous Latch Enabled Controlled Write 38/53 ...
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... Table 28. Program, Erase Times and Program Erase Endurance Cycles ( 2.7V to 3.6V Parameters Uniform Block (1Mb) Erase Chip Program Write Buffer Program Suspend Latency Time Erase Suspend Latency Time Program/Erase Cycles (per Block) M58LW064A, M58LW064B = 1. Parameter Min 500 =1.7V to 1.9V) DDQ M58LW064A/B Min Max Typ 1 ...
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... M58LW064A, M58LW064B Figure 19. Reset, Power-down and Power-up AC Waveform DDQ E 40/53 Reset during Read Mode tPLPH tPHQV Reset Recovery to Read Reset during Program/Erase tPHWL tPLRH tPHEL tPLPH Reset Recovery Abort tPHWL tPLRH tPHEL tPLPH Power Abort Recovery Down Reset during Power up ...
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... Figure 20. Write Buffer Program Flowchart and Pseudo Code M58LW064A, M58LW064B Start Write to Buffer E8h Command, Block Address Read Status Register NO NO Write to Buffer Timeout YES Write Word or Byte Count, Block Address Write Buffer Data, Start Address YES Write Next Buffer Data, ...
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... M58LW064A, M58LW064B Figure 21. Program Suspend & Resume Flowchart and Pseudo Code Start Write B0h Command Write 70h Command Read Status Register YES YES Write FFh Command Read data from another block Write D0h Command Program Continues 42/53 PES instruction: – write B0h command ...
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... YES YES End Note error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations. M58LW064A, M58LW064B EE instruction: – write 20h command – write Block Address (A12-A17) & command D0h (memory enters read status state after the EE instruction) ...
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... M58LW064A, M58LW064B Figure 23. Erase Suspend & Resume Flowchart and Pseudo Code Start Write B0h Command Write 70h Command Read Status Register YES YES Write FFh Command Read data from another block or Program Write D0h Command Program Continues 44/53 PES instruction: – ...
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... Command Interface defaults to Read Array mode. DD LKO 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7. NO 70h YES READ NO 50h YES CLEAR NO E8h STATUS YES PROGRAM BUFFER LOAD C M58LW064A, M58LW064B READ ARRAY NO 20h YES ERASE NO FFh SET-UP YES NO D0h YES ERASE A COMMAND ERROR AI03618 45/53 ...
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... M58LW064A, M58LW064B Figure 25. Command Interface and Program Erase Controller Flowchart ( YES READ STATUS YES READ SIGNATURE YES CFI QUERY PROGRAM YES BUFFER LOAD c NO READ ARRAY AI03618 Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7. 46/53 A ERASE YES READY (2) NO ...
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... Figure 26. Command Interface and Program Erase Controller Flowchart ( PROGRAM SUSPENDED YES READ STATUS YES READ SIGNATURE YES CFI QUERY NO READ ARRAY AI00618 Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7. M58LW064A, M58LW064B C PROGRAM YES READY (2) NO B0h YES PROGRAM SUSPEND YES READY (2) NO READ STATUS YES 70h ...
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... M58LW064A, M58LW064B Table 29. Ordering Information Scheme Example: Device Type M58 Architecture L = Multi-Bit Cell, Burst Mode, Page Mode Operating Voltage 2.7V to 3.6V 1 DDQ Device Function 064A = 64 Mbit (x16), Equal Block, Boot Block 064B = 64 Mbit (x16/x32), Equal Block, Boot Block Speed 150 = 150 ns ...
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... Drawing is not to scale. mm Min Max Typ 1.20 0.05 0.15 0.95 1.05 0.17 0.27 0.10 0.21 20.20 18.50 14.10 – – 0.0197 0. M58LW064A, M58LW064B inches Min Max 0.0472 0.0020 0.0059 0.0374 0.0413 0.0067 0.0106 0.0039 0.0083 0.7795 0.7953 0.7205 0.7283 0.5472 0.5551 – – 0.0197 0.0276 0.0039 ...
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... M58LW064A, M58LW064B Table 31. TSOP86 Type II, Package Mechanical Data Symbol Typ A A1 0.050 A2 0.950 b 0.220 0.170 C 0.145 D 22.220 22.120 E 11.760 11.560 E1 10.160 10.060 e 0.500 L 0.450 N CP Figure 28. TSOP86 Type II, Package Outline Drawing is not to scale. 50/53 mm Min Max Typ 1.200 1.150 0.300 0.0087 – ...
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... M58LW064A, M58LW064B inches Min Max 0.1339 0.0098 0.1004 0.1201 0.0118 0.0177 0.0043 0.0091 – – – – – – – – – – 0.0287 0.0406 0 7 ...
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... M58LW064A, M58LW064B Table 33. LBGA54 - balls pitch, Package Mechanical Data Symbol Typ A 1.090 0.980 A1 0.290 0.220 A2 0.800 0.760 b 0.430 0.300 D 10.000 9.800 D1 7.000 ddd e 1.000 0.925 E 13.000 12.800 E1 7.000 FD 3.000 FE 1.500 SD 0.500 SE 0.500 Figure 30. LBGA54 - balls pitch, Package Outline ...
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