XC68HC705JB3 Motorola, XC68HC705JB3 Datasheet - Page 41

• Manufacturer Part Number: XC68HC705JB3
• Description: MICROCONTROLLER
• Manufacturer: Motorola

5.3.2 USB Reset
5.3.3 Computer Operating Properly (COP) Reset
5.3.4 Low Voltage Reset (LVR)
MC68HC05JB3
REV 1
The POR will generate the RST signal which will reset the CPU. If any other reset
function is active at the end of the 224 or 4064 cycle delay, the RST signal will
remain in the reset condition until the other reset condition(s) end.
POR will not activate the pulldown device on the RESET pin. V
below V
The USB reset is generated by a detection on the USB bus reset signal. For
MC68HC05JB3, seeing a single-end zero on its upstream port for 4 to 8 bit times
will set RSTF bit in UIR0 register. The detections will also generate the RST signal
to reset the CPU and other peripherals in the MCU.
The COP watchdog is enabled by a mask option.
A timeout of the COP watchdog generates a COP reset. The COP watchdog is
part of a software error detection system and must be cleared periodically to start
a new timeout period. To clear the COP watchdog and prevent a COP reset, write
a logic zero to the COPC bit of the COP register at location $1FF0.
COPC — COP Clear
The COP Watchdog reset will assert the pull-down device to pull the RESET pin
low for one cycle of the internal bus clock.
Refer to section on Multi-Function Timer for detail on COP watchdog timeout peri-
ods.
The LVR activates the RST reset signal to reset the device when the voltage on
the V
device to pull the RESET pin low one cycle of the internal bus clock. The Low Volt-
age Reset circuit is enabled by a mask option.
COPR
$1FF0
U = UNAFFECTED BY RESET
COPC is a write-only bit. Periodically writing a logic zero to COPC prevents the
COP watchdog from resetting the MCU. Reset clears the COPC bit.
reset:
1 = No effect on system.
0 = Reset COP watchdog timer.
DD
POR
W
pin falls below the LVR trip voltage. The LVR will assert the pulldown
R
in order for the internal POR circuit to detect the next rise of V
BIT 7
U
0
Figure 5-2. COP Watchdog Register (COPR)
BIT 6
U
0
November 5, 1998
BIT 5
U
0
RESETS
BIT 4
U
0
GENERAL RELEASE SPECIFICATION
BIT 3
U
0
BIT 2
U
0
BIT 1
DD
U
0
MOTOROLA
must drop
DD
COPC
BIT 0
.
0
0
5-3