ST92T163 ST Microelectronics, ST92T163 Datasheet - Page 183

• Manufacturer Part Number: ST92T163
• Description: 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS
• Manufacturer: ST Microelectronics

I
8.5.5 Interrupt Features
The I
related to “Error Condition”, “Peripheral Ready to
Transmit” and “Data Received”.
The peripheral uses the ST9+ interrupt internal
protocol without requiring the use of the external
interrupt channel. Dedicated registers of the pe-
ripheral should be loaded with appropriate values
to set the interrupt vector (see the description of
the I2CIVR register), the interrupt mask bits (see
the description of the I2CIMR register) and the in-
terrupt priority and pending bits (see the descrip-
tion of the I2CISR register).
The peripheral also has a global interrupt enable
(the I2CCR.ITE bit) that must be set to enable the
interrupt features. Moreover there is a global inter-
rupt flag that is set when one of the interrupt
events occurs (except the End Of Block interrupts
- see the DMA Features section).
The “Data Received” interrupt source occurs after
the acknowledge of a received data byte is per-
formed. It is generated when the I2CSR1.BTF flag
is set and the I2CSR1.TRA flag is zero.
If the DMA feature is enabled in receiver mode,
this interrupt is not generated and the same inter-
rupt vector is used to send a Receiving End Of
Block interrupt (See the DMA feature section).
The “Peripheral Ready To Transmit” interrupt
source occurs as soon as a data byte can be
transmitted by the peripheral. It is generated when
the I2CSR1.BTF and the I2CSR1.TRA flags are
set.
If the DMA feature is enabled in transmitter mode,
this interrupt is not generated and the same inter-
rupt vector is used to send a Transmitting End Of
Block interrupt (See the DMA feature section).
The “Error condition” interrupt source occurs when
one of the following condition occurs:
2
C INTERFACE (Cont’d)
– Address matched in Slave mode while
– Start condition generated
– No acknowledge received after byte transmis-
– Stop detected in Slave mode
I2CCR.ACK=1
(I2CSR1.ADSL and I2CSR1.EVF flags = 1)
(I2CSR1.SB and I2CSR1.EVF flags = 1)
sion
(I2CSR2.AF and I2CSR1.EVF flags = 1)
(I2CSR2.STOPF and I2CSR1.EVF flags = 1)
2
Cbus interface has three interrupt sources
Note: Depending on the value of I2CISR.DMAS-
TOP bit, the pending bit related to the “error condi-
tion” interrupt source is able to suspend or not sus-
pend DMA transfers.
Each interrupt source has a dedicated interrupt
address pointer vector stored in the I2CIVR regis-
ter. The five more significant bits of the vector ad-
dress are programmable by the customer, where-
as the three less significant bits are set by hard-
ware depending on the interrupt source:
– 010: error condition detected
– 100: data received
– 110: peripheral ready to transmit
The priority with respect to the other peripherals is
programmable by setting the PRL[2:0] bits in the
I2CISR register. The lowest interrupt priority is ob-
tained by setting all the bits (this priority level is
never acknowledged by the CPU and is equivalent
to disabling the interrupts of the peripheral); the
highest interrupt priority is programmed by reset-
ting all the bits. See the Interrupt and DMA chap-
ters for more details.
The internal priority of the interrupt sources of the
peripheral is fixed by hardware with the following
order: “Error Condition” (highest priority), “Data
Received”, “Peripheral Ready to Transmit”.
Note: The DMA has the highest priority over the
interrupts; moreover the “Transmitting End Of
Block” interrupt has the same priority as the “Pe-
ripheral Ready to Transmit” interrupt and the “Re-
ceiving End Of Block” interrupt has the same prior-
ity as the “Data received” interrupt.
Each of these three interrupt sources has a pend-
ing bit (IERRP, IRXP, ITXP) in the I2CISR register
that is set by hardware when the corresponding in-
terrupt event occurs. An interrupt request is per-
formed only if the corresponding mask bit is set
(IERRM, IRXM, ITXM) in the I2CIMR register and
the peripheral has a proper priority level.
The pending bit has to be reset by software.
– Arbitration lost in Master mode
– Bus error, Start or Stop condition detected
– Master has sent the header byte
– Address byte successfully transmitted in
(I2CSR2.ARLO and I2CSR1.EVF flags = 1)
during data transfer
(I2CSR2.BERR and I2CSR1.EVF flags = 1)
(I2CSR1.ADD10 and I2CSR1.EVF flags = 1)
Master mode.
(I2CSR1.EVF = 1 and I2CSR2.ADDTX=1)
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