ST92T163 ST Microelectronics, ST92T163 Datasheet - Page 184

• Manufacturer Part Number: ST92T163
• Description: 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS
• Manufacturer: ST Microelectronics

ST92163 - I2C BUS INTERFACE
I
Note: Until the pending bit is reset (while the cor-
responding mask bit is set), the peripheral proc-
esses an interrupt request. So, if at the end of an
interrupt routine the pending bit is not reset, anoth-
er interrupt request is performed.
Note: Before the end of the transmission and re-
ception interrupt routines, the I2CSR1.BTF flag bit
should be checked, to acknowledge any interrupt
requests that occurred during the interrupt routine
and to avoid masking subsequent interrupt re-
quests.
Note: The “Error” event interrupt pending bit
(I2CISR.IERRP) is forced high until the error event
flags are set (ADD10, ADSL and SB flags of the
I2CSR1 register; SCLF, ADDTX, AF, STOPF,
ARLO and BERR flags of the I2CSR2 register).
Note: If the I2CISR.DMASTOP bit is reset, then
the DMA has the highest priority with respect to
the interrupts; if the bit is set (as after the MCU re-
set) and the “Error event” pending bit is set
(I2CISR.IERRP), then the DMA is suspended until
the pending bit is reset by software. In the second
case, the “Error” interrupt sources have higher pri-
ority, followed by DMA, “Data received” and “Re-
ceiving End Of Block” interrupts, “Peripheral
Ready to Transmit” and “Transmitting End Of
Block”.
Moreover the Transmitting End Of Block interrupt
has the same priority as the “Peripheral Ready to
Transmit” interrupt and the Receiving End Of
Block interrupt has the same priority as the “Data
received” interrupt.
8.5.6 DMA Features
The peripheral can use the ST9+ on-chip Direct
Memory Access (DMA) channels to provide high-
speed data transaction between the peripheral
and contiguous locations of Register File, and
Memory. The transactions can occur from and to-
ward the peripheral. The maximum number of
transactions that each DMA channel can perform
is 222 if the register file is selected or 65536 if
memory is selected. The control of the DMA fea-
tures is performed using registers placed in the pe-
ripheral
I2CRDAP, I2CRDC, I2CTDAP, I2CTDC).
Each DMA transfer consists of three operations:
– A load from/to the peripheral data register
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C INTERFACE (Cont’d)
(I2CDR) to/from a location of Register File/Mem-
register
page
(I2CISR,
I2CIMR,
– A post-increment of the DMA Address Register
– A post-decrement of the DMA transaction coun-
Depending on the value of the DDCISR.DMAS-
TOP bit the DMA feature can be suspended or not
(both in transmission and in reception) until the
pending bit related to the “Error event” interrupt re-
quest is set.
The priority level of the DMA features of the I
interface with respect to the other peripherals and
the CPU is the same as programmed in the
I2CISR register for the interrupt sources. In the in-
ternal priority level order of the peripheral, if DD-
CISR.DMASTOP=0, DMA has a higher priority
with respect to the interrupt sources. Otherwise (if
DDCISR.DMASTOP=1), the DMA has a priority
lower than “error” event interrupt sources but
greater than reception and transmission interrupt
sources.
Refer to the Interrupt and DMA chapters for details
on the priority levels.
The DMA features are enabled by setting the cor-
responding enabling bits (RXDM, TXDM) in the
I2CIMR register. It is possible to select also the di-
rection of the DMA transactions.
Once the DMA transfer is completed (the transac-
tion counter reaches 0 value), an interrupt request
to the CPU is generated. This kind of interrupt is
called “End Of Block”. The peripheral sends two
different “End Of Block” interrupts depending on
the direction of the DMA (Receiving End Of Block -
Transmitting End Of Block). These interrupt
sources have dedicated interrupt pending bits in
the I2CIMR register (REOBP, TEOBP) and they
are mapped on the same interrupt vectors as re-
spectively “Data Received” and “Peripheral Ready
to Transmit” interrupt sources. The same corre-
spondence exists about the internal priority be-
tween interrupts.
Note: The I2CCR.ITE bit has no effect on the End
Of Block interrupts.
Moreover, the I2CSR1.EVF flag is not set by the
End Of Block interrupts.
ory addressed through the DMA Address Regis-
ter (or Register pair)
(or Register pair)
ter, which contains the number of transactions
that have still to be performed.
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