COP8SG National Semiconductor, COP8SG Datasheet
COP8SG
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COP8SG Summary of contents
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... These single-chip CMOS devices are suited for more complex applications re- quiring a full featured controller with larger memory, low EMI, two comparators, and a full-duplex USART. COP8SGx7 de- vices are 100% form-fit-function compatible 8k or 32k OTP (One Time Programmable) versions for use in production or development ...
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... Two power saving modes: HALT and IDLE Temperature Range n −40˚C to +85˚C, −40˚C to +125˚C Development Support n Windowed packages for DIP and PLCC n Real time emulation and full program debug offered by ® MetaLink Development System FIGURE 1. COP8SGx Block Diagram 2 < 4 µA) DS101317-44 ...
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... EXCHANGE). And 15 memory-maped registers allow de- signers to optimize the precise implementation of certain specific instructions. 1.3 EMI REDUCTION The COP8SGx5 family of devices incorporates circuitry that guards against electromagnetic interference — an increasing problem in today’s microcontroller board designs. National’s patented EMI reduction technology offers low EMI clock cir- ...
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... See NS Package Number D28JQ Top View Order Number COP8SGXY44V8 See NS Package Number V44A Order Number COP8SGR744J3 See NS Package Number EL44C www.national.com Order Number COP8SGXY40N8 See NS Package Number N40A Order Number COP8SGR540Q3 See NS Package Number D40KQ DS101317-6 Order Number COP8SGXYVEJ8 See NS Package Number VEJ44A FIGURE 2 ...
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Connection Diagrams (Continued) Pinouts for 28 -, 40- and 44-Pin Packages Port Type Alt. Fun L0 I/O MIWU L1 I/O MIWU or CKX L2 I/O MIWU or TDX L3 I/O MIWU or RDX L4 I/O MIWU or T2A L5 I/O ...
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Ordering Information www.national.com FIGURE 3. Part Numbering Scheme 6 DS101317-8 ...
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... Electrical Characteristics Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin Total Current into V CC Pin (Source) DC Electrical Characteristics −40˚C T +85˚C unless otherwise specified. ...
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DC Electrical Characteristics −40˚C T +85˚C unless otherwise specified. A Parameter Output Current Levels D Outputs Source Sink All Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage Allowable Sink Current per Pin (Note 9) D ...
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... ESD transients. Note 8: National Semiconductor uses the High Temperature Storage Life (HTSL) test to evaluate the data retention capabilities of the EPROM memory cells used in our OTP microcontrollers. Qualification devices have been stressed at 150˚C for 1000 hours. Under these conditions, our EPROM cells exhibit data retention ca- pabilities in excess of 29 years. This is based on an activation energy of 0.7eV derated to 55˚ ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin Total Current into V CC Pin (Source) DC Electrical Characteristics −40˚C T +125˚C unless otherwise specified. ...
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DC Electrical Characteristics −40˚C T +125˚C unless otherwise specified. A Parameter EPROM Data Retenton (Note 8),(Note 9) Input Capacitance Load Capacitance Electrical Characteristics −40˚C T +125˚C unless otherwise specified. A Parameter Instruction Cycle Time ( ...
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Typical Performance Characteristics www.national.com = 25˚C (unless otherwise specified DS101317-49 DS101317-51 12 DS101317-50 DS101317-52 ...
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... Pin Descriptions The COP8SGx I/O structure enables designers to reconfig- ure the microcontroller’s I/O functions with a single instruc- tion. Each individual I/O pin can be independently configured as output pin low, output high, input with high impedance or input with weak pull-up device. A typical example is the use of I/O pins as the keyboard matrix input lines ...
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... Port F input pins (address xx96 recommended new applications which will go to production with the COP8SGx use the Port F addresses. Note that compatible ROM devices contains the input only Port I instead of the bi-directional Port F ...
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Functional Description memory mapped; therefore, I/O bits and register bits can be directly and individually set, reset and tested. The accumula- tor (A) bits can also be directly and individually tested. Note: RAM contents are undefined upon power-up. 5.4 ...
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... Functional Description Memory address ranges 0200 to 027F and 0300 to 037F are unavailable on the COP8SGx5 and, if read, will return under- fined data. 5.5 ECON (CONFIGURATION) REGISTER For compatibility with COP8SGx7 devices, mask options are defined by an ECON Configuration Register which is pro- grammed at the same time as the program code. Therefore, the register is programmed at the same time as the program memory ...
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Functional Description FIGURE 9. Reset Logic The following occurs upon initialization: Port L: TRI-STATE (High Impedance Input) Port C: TRI-STATE (High Impedance Input) Port G: TRI-STATE (High Impedance Input) Port F: TRI-STATE (High Impedance Input) Port D: HIGH PC: ...
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Functional Description FIGURE 11. Reset Timing (Power-On Reset Enabled) with V Tied to RESET CC DS101317-16 FIGURE 12. Reset Circuit Using Power-On Reset 5.10 OSCILLATOR CIRCUITS There are four clock oscillator options available: Crystal Os- cillator with or without ...
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Functional Description With On-Chip Bias Resistor DS101317-17 DS101317-20 For operation at lower than maximum R/C oscillator frequency. (Continued) Without On-Chip Bias Resistor FIGURE 13. Crystal Oscillator DS101317-19 FIGURE 14. External Oscillator For operation at maximum R/C oscillator frequency. FIGURE ...
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Functional Description 5.11 CONTROL REGISTERS CNTRL Register (Address X'00EE) T1C3 T1C2 T1C1 T1C0 MSEL Bit 7 The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits: T1C3 Timer T1 mode control bit T1C2 Timer T1 mode control bit ...
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Timers (Continued) • Timing the width of the internal power-on-reset The IDLE Timer T0 can generate an interrupt when the twelfth bit toggles. This toggle is latched into the T0PND pending flag, and will occur every 2.731 ms at ...
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Timers (Continued) In this mode the input pin TxB can be used as an indepen- dent positive edge sensitive interrupt input if the TxENB con- trol flag is set. The occurrence of a positive edge on the TxB input ...
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Timers (Continued) 6.3 TIMER CONTROL FLAGS The control bits and their functions are summarized below. TxC3 Timer mode control TxC2 Timer mode control TxC1 Timer mode control TxC0 Timer Start/Stop control in Modes 1 and 2 (Pro- cessor Independent ...
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Power Saving Features Today, the proliferation of battery-operated based applica- tions has placed new demands on designers to drive power consumption down. Battery-operated systems are not the only type of applications demanding low power. The power budget constraints are ...
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Power Saving Features 7.2 IDLE MODE The device is placed in the IDLE mode by writing a “1” to the IDLE flag (G6 data bit). In this mode, all activities, except the associated on-board oscillator circuitry and the IDLE ...
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Power Saving Features 7.3 MULTI-INPUT WAKEUP The Multi-Input Wakeup feature is used to return (wakeup) the device from either the HALT or IDLE modes. Alternately Multi-Input Wakeup/Interrupt feature may also be used to generate edge selectable ...
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USART Each device contains a full-duplex software programmable USART. The USART ( Figure 22 ) consists of a transmit shift register, a receive shift register and seven addressable reg- isters, as follows: a transmit buffer register (TBUF), a re- ...
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USART (Continued) 8.1 USART CONTROL AND STATUS REGISTERS The operation of the USART is programmed through three registers: ENU, ENUR and ENUI. 8.2 DESCRIPTION OF USART REGISTER BITS ENU-USART Control and Status Register (Address at 0BA) PEN PSEL1 XBIT9/ ...
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USART (Continued) ETI: This bit enables/disables interrupt from the transmitter section. Read/Write, cleared on reset. ETI = 0 Interrupt from the transmitter is disabled. ETI = 1 Interrupt from the transmitter is enabled. 8.3 Associated I/O Pins Data is ...
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USART (Continued) 8.6 USART INTERRUPTS The USART is capable of generating interrupts. Interrupts are generated on Receive Buffer Full and Transmit Buffer Empty. Both interrupts have individual interrupt vectors. Two bytes of program memory space are reserved for each ...
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USART (Continued) FIGURE 25. USART BAUD Clock Divisor Registers TABLE 4. Baud Rate Divisors (1.8432 MHz Prescaler Output) Baud Baud Rate Rate Divisor − 1 (N-1) 110 1046 (110.03) 134.5 855 (134.58) 150 767 300 383 600 191 1200 ...
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USART (Continued example, considering Asynchronous Mode and a CKI clock of 4.608 MHz, the prescaler factor selected is: 4.608/1.8432 = 2.5 The 2.5 entry is available in Table 5 . The 1.8432 MHz pres- caler output is ...
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Comparators The device contains two differential comparators, each with a pair of inputs (positive and negative) and an output. Ports F1–F3 and F4–F6 are used for the comparators. The follow- ing is the Port F assignment: F6 Comparator2 output ...
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Interrupts (Continued) 10.2 MASKABLE INTERRUPTS All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated enable bit and pending flag bit. The pending bit is set to 1 when the interrupt condition occurs. The ...
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Interrupts (Continued) ample, if the Software Trap routine is located at 0310 Hex, then the vector location 0yFE and -0yFF should contain the data 03 and 10 Hex, respectively. When a Software Trap in- terrupt occurs and the VIS ...
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Interrupts (Continued) 10.3.1 VIS Execution When the VIS instruction is executed it activates the arbitra- tion logic. The arbitration logic generates an even number between E0 and FE (E0, E2, E4, E6 etc...) depending on which active interrupt has ...
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Interrupts (Continued) FIGURE 28. VIS Flowchart 37 DS101317-30 www.national.com ...
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Interrupts (Continued) Programming Example: External Interrupt PSW =00EF CNTRL =00EE RBIT 0,PORTGC RBIT 0,PORTGD SBIT IEDG, CNTRL SBIT EXEN, PSW SBIT GIE, PSW WAIT: JP WAIT . . . .=0FF VIS . . . .=01FA .ADDRW SERVICE . . ...
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Interrupts (Continued) 10.4 NON-MASKABLE INTERRUPT 10.4.1 Pending Flag There is a pending flag bit associated with the non-maskable interrupt, called STPND. This pending flag is not memory- mapped and cannot be accessed directly by the software. The pending flag ...
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WATCHDOG/Clock Monitor Each device contains a user selectable WATCHDOG and clock monitor. The following section is applicable only if WATCHDOG feature has been selected in the ECON regis- ter. The WATCHDOG is designed to detect the user program getting ...
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WATCHDOG/Clock Monitor Key Window Data Data Match Match Don’t Care Mismatch Mismatch Don’t Care Don’t Care Don’t Care 11.3 WATCHDOG AND CLOCK MONITOR SUMMARY The following salient points regarding the WATCHDOG and CLOCK MONITOR should be noted: • Both ...
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MICROWIRE/PLUS MICROWIRE/PLUS is a serial SPI compatible synchronous communications interface. The MICROWIRE/PLUS capabil- ity enables the device to interface with MICROWIRE/PLUS or SPI peripherals (i.e. A/D converters, display drivers, EE- PROMs etc.) and with other microcontrollers which support the ...
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MICROWIRE/PLUS 12.1.2 MICROWIRE/PLUS Slave Mode Operation In the MICROWIRE/PLUS Slave mode of operation the SK clock is generated by an external source. Setting the MSEL bit in the CNTRL register enables the SO and SK functions onto the G ...
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MICROWIRE/PLUS FIGURE 32. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High FIGURE 33. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being High www.national.com (Continued) 44 DS101317-35 DS101317-31 ...
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... COP8SGE) 0300–037F On-Chip 128 RAM Bytes (Reads as undefined data on COP8SGE) Note: Reading memory locations 0070H–007FH (Segment 0) will return all ones. Reading unused memory locations 0080H–0093H (Segment 0) will return undefined data. Reading memory locations from other Seg- ments (i.e., Segment 4, Segment 5, … ...
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Instruction Set 14.1 INTRODUCTION This section defines the instruction set of the COPSAx7 Family members. It contains information about the instruc- tion set features, addressing modes and types. 14.2 INSTRUCTION FEATURES The strength of the instruction set is based ...
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Instruction Set (Continued) Example: Load Accumulator Immediate Reg/Data Contents Memory Before Accumulator XX Hex Immediate Short. This is a special case of an immediate in- struction. In the “Load B immediate” instruction, the 4-bit im- ...
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Instruction Set (Continued) Jump Indirect. In this 1-byte instruction, the lower byte of the jump address is obtained from a table stored in program memory, with the Accumulator serving as the low order byte of a pointer into program ...
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Instruction Set (Continued) 14.4.9 No-Operation Instruction The no-operation instruction does nothing, except to occupy space in the program memory and time in execution. No-Operation (NOP) Note: The VIS is a special case of the Indirect Transfer of Control addressing ...
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Instruction Set (Continued) ± LoaD A with Memory [B] ± LoaD A with Memory [X] ± ],Imm LoaD Memory [B] Immed. CLR A CLeaR A INC A INCrement A ...
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Instruction Set (Continued) 14.7 INSTRUCTION EXECUTION TIME Most instructions are single byte (with immediate addressing mode instructions taking two bytes). Most single byte instructions take one cycle time to execute. Skipped instructions require x number of cycles to be ...
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Instruction Set (Continued) www.national.com Nibble Lower 52 ...
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... Includes COP8-NSDEV, Drive- way COP8 Demo, MetaLink Debugger, I/O cables and power supply. • COP8–EVAL: Very Low cost evaluation and design test board for COP8ACC and COP8SGx Families, from ICU. Real-time environment with add-on A/D, D/A, and EE- PROM. Includes software routines and reference de- signs. ...
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... Call MetaLink www.national.com 16.3 TOOLS ORDERING NUMBERS FOR THE (Continued) COP8SGx FAMILY DEVICES The COP8SG-DM and IM-COP8/400 ICE can be used for emulation with the limitation of 10 MHz emulation speed maximum. For full speed COP8SGx emulation, use the 15 MHz COP8SG-DM5. Order Number Cost ...
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... DM-COP8/xxx (ie. 28D) DM Target MHW-CNVxx (xx = 33, 34 Adapters etc.) OTP MHW-COP8-PGMA-DS Programming Adapters MHW-COP8-PGMA-44QFP L MHW-COP8-PGMA-28CSP L IM-COP8 IM-COP8-AD-464 (-220) (10 MHz maximum) IM Probe Card PC-COP8SG44PW-AD-10 PC-COP8SG40DW-AD-10 IM Probe Target MHW-SOICxx (xx = 16, Adapters 20, 28) MHW-CSPxx (xx = 20, 28) MHW-CONV33 COP8-EVAL-ICUxx ICU-303 ICU or National COP8-EVAL KKD WCOP8-IDE WCOP8-IDE IAR ...
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Development Support 16.4 WHERE TO GET TOOLS Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors. Vendor Home Office Aisys U.S.A.: Santa Clara, CA 1-408-327-8820 fax: 1-408-327-8830 Byte ...
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... Physical Dimensions inches (millimeters) unless otherwise noted Molded SO Wide Body Package (WM) Order Number COP8SGx528Mx, NS Package Number M28B Molded Dual-In-Line Package (N) Order Number COP8SGx728Nx NS Package Number N28A 57 www.national.com ...
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... Physical Dimensions www.national.com inches (millimeters) unless otherwise noted (Continued) Molded Dual-In-Line Package (N) Order Number COP8SGx540Nx NS Package Number N40A 58 ...
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... Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 44-Lead EPROM Leaded Chip Carrier (EL) Order Number COP8SGR744J3 NS Package Number EL44C 59 www.national.com ...
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... Physical Dimensions www.national.com inches (millimeters) unless otherwise noted (Continued) Molded Dual-In-Line Package (N) Order Number COP8SGx544Vx NS Package Number V44A Plastic Quad Flat Package (VEJ) Order Number COP8SGx544VEJx NS Package Number VEJ44A 60 ...
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... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...