COP8SG National Semiconductor, COP8SG Datasheet - Page 17

• Manufacturer Part Number: COP8SG
• Description: 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory/ Two Comparators and USART
• Manufacturer: National Semiconductor

5.0 Functional Description
The following occurs upon initialization:
DOG logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are in-
hibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t
being initialized high will cause a Clock Monitor error follow-
ing reset if the clock has not reached the minimum specified
Port L: TRI-STATE (High Impedance Input)
Port C: TRI-STATE (High Impedance Input)
Port G: TRI-STATE (High Impedance Input)
Port F: TRI-STATE (High Impedance Input)
Port D: HIGH
PC: CLEARED to 0000
PSW, CNTRL and ICNTRL registers: CLEARED
SIOR:
T2CNTRL: CLEARED
T3CNTRL: CLEARED
Accumulator, Timer 1, Timer 2 and Timer 3:
WKEN, WKEDG: CLEARED
WKPND: RANDOM
SP (Stack Pointer):
B and X Pointers:
S Register: CLEARED
RAM:
USART:
COMPARATORS:
WATCHDOG (if enabled):
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
RANDOM after RESET with crystal clock option
(power already applied)
UNAFFECTED after RESET with R/C clock option
(power already applied)
RANDOM after RESET at power-on
Initialized to RAM address 06F Hex
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
PSR, ENU, ENUR, ENUI: Cleared except the TBMT bit
which is set to one.
CMPSL; CLEARED
The device comes out of reset with both the WATCH-
FIGURE 9. Reset Logic
C
clock cycles. The Clock Monitor bit
DS101317-13
(Continued)
17
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
output will continue until 16 t
the clock frequency reaching the minimum specified value,
at which time the G1 output will go high.
5.9.1 External Reset
The RESET input when pulled low initializes the device. The
RESET pin must be held low for a minimum of one instruc-
tion cycle to guarantee a valid reset. During Power-Up initial-
ization, the user must ensure that the RESET pin is held low
until the device is within the specified V
circuit on the RESET pin with a delay 5 times (5x) greater
than the power supply rise time or 15 µs whichever is
greater, is recommended. Reset should also be wide enough
to ensure crystal start-up upon Power-Up.
RESET may also be used to cause an exit from the HALT
mode.
A recommended reset circuit for this device is shown in Fig-
ure 10 .
RC
5.9.2 On-Chip Power-On Reset
The on-chip reset circuit is selected by a bit in the ECON reg-
ister. When enabled, the device generates an internal reset
as V
circuitry is able to detect both fast and slow rise times on V
(V
on-chip power-on-reset, V
the start voltage specified in the DC characteristics. Also, if
V
to the operating range. If this is not possible, it is recom-
mended that external reset be used.
Under no circumstances should the RESET pin be allowed
to float. If the on-chip Power-On Reset feature is being used,
RESET pin should be connected directly, or through a
pull-up resistor, to V
tector will always preset the Idle timer to 0FFF(4096 t
this time, the internal reset will be generated.
If the Power-On Reset feature is enabled, the internal reset
will not be turned off until the Idle timer underflows. The inter-
nal reset will perform the same functions as external reset.
The user is responsible for ensuring that V
mum level for the operating frequency within the 4096 t
ter the underflow, the logic is designed such that no addi-
tional internal resets occur as long as V
2.0V.
The contents of data registers and RAM are unknown follow-
ing the on-chip reset.
CC
CC
>
5x power supply rise time or 15 µs, whichever is greater.
CC
FIGURE 10. Reset Circuit Using External Reset
be lowered to the start voltage before powering back up
rise time between 10 ns and 50 ms).To guarantee an
rises to a voltage level above 2.0V. The on-chip reset
CC
. The output of the power-on reset de-
CC
must start at a voltage less than
C
–32 t
C
clock cycles following
CC
CC
DS101317-14
CC
voltage. An R/C
remains above
is at the mini-
www.national.com
C
C
). At
. Af-
CC