M40Z300W ST Microelectronics, M40Z300W Datasheet - Page 5

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M40Z300W

Manufacturer Part Number
M40Z300W
Description
NVRAM CONTROLLER for up to EIGHT LPSRAM
Manufacturer
ST Microelectronics
Datasheet

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Figure 4. Hardware Hookup
POWER-ON RESET OUTPUT
All microprocessors have a reset input which forc-
es them to a known state when starting. The
M40Z300/W has a reset output (RST) pin which is
guaranteed to be low within t
ble 7). This signal is an open drain configuration.
An appropriate pull-up resistor should be chosen
to control the rise time. This signal will be valid for
all voltage conditions, even when V
3.0V, 3.3V or 5V
Threshold
0.1 F
V CC
A
B
E
THS
V SS
M40Z300W
M40Z300
E1 CON
E2 CON
E3 CON
E4 CON
V OUT
RST
BL
WPT
0.1 F
To Microprocessor
To Battery Monitor Circuit
of V
CC
V CC
E
CMOS
PFD
SRAM
equals V
(See Ta-
SS
0.1 F
.
V CC
Once V
age V
t
TWO TO FOUR DECODE
The M40Z300/W includes a 2 input (A, B) decoder
which allows the control of up to 4 independent
SRAMs. The Truth Table for these inputs is shown
in Table 3.
E
REC
CMOS
SRAM
to allow the power supply to stabilize.
PFD
CC
, an internal timer keeps RST low for
exceeds the power failure detect volt-
0.1 F
V CC
E
CMOS
SRAM
M40Z300, M40Z300W
0.1 F
V CC
AI02395
E
CMOS
SRAM
5/16

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