XR2212 Exar Corporation, XR2212 Datasheet - Page 12

• Manufacturer Part Number: XR2212
• Description: Precision Phase-Locked Loop
• Manufacturer: Exar Corporation

Recommended values of bandwidth ratio, N, for various
values of FM signal frequency deviation. (Note: N is the
ratio of tracking bandwidth
deviation, f
f)
Design Example
Demodulator for FM signal with 67kHz carrier frequency
with
and required peak output swing is
Step a)
Step b)
Step c)
Step d)
XR-2212
Calculate R
amplitude. Output signal amplitude, V
as:
In most applications, R
then R
to give desired output swing. The output amplifier can
also be used as a unity-gain voltage follower, by open
circuiting R
Note: All calculated component values except R
rounded-off to the nearest
varied to fine-tune center frequency, through a series
potentiometer, R
Rev. 2.01
% Deviation of FM
Signal ( f
5kHz frequency deviation. Supply voltage is +12V
10% to 30%
30% to 50%
5% to 10%
1% or less
1% to 3%
1% to 5%
f
Choose R
series with 5k
Calculate C
C
Calculate R
Then:
0
C
0
f
, can be calculated from the above equation
is chosen as 67kHz.
SM
SM
= 746pF
V
OUT
/f
).
C
SM
0
C
(i.e., R
= 0.0746, and N = 3 from Table 2.
/f
and R
X
0
0
, (See Figure 11).
)
= 20k
0
1
; from design equation (1).
. For given FM deviation,
Table 2.
f
C
f
0
SM
F
= ).
potentiometer).
F
standard value, and R
to set peak output signal
( V
= 100k
f to max. signal frequency
(18k
Recommended Value of
REF
Bandwidth Ratio, N
) R
R
(N =
fixed resistor in
1
0
4V.
is recommended;
R
1.5
10
5
4
3
2
f
C
OUT
/
R
f
C
SM
, is given
R
F
)
0
0
can be
can be
12
Step e): Calculate C1 = (C
Step f):
Note: All values except R
FREQUENCY SYNTHESIS
Figure 12 shows the generalized circuit connection for
frequency synthesis. In this application an external
frequency divider is connected between the VCO output
(Pin 5) and the phase-detector input (Pin 16). When the
circuit is in lock, the two signals going into the
phase-detector are at the same frequency, or f
where N is the modulus of the external frequency divider.
Conversely, the VCO output frequency, f
In the circuit configuration of Figure 12 , the external
timing components, R
frequency; R
loop damping, i.e., the low-pass filter time constant (see
design equations).
The total tracking range of the PLL (see Figure 10 ),
should be chosen to accommodate the lowest and the
highest frequency, f
recommended choice for most applications is to choose a
tracking half-bandwidth f, such that:
If a variable input frequency and a variable counter
modulus N is used, then the maximum and the minimum
values of output frequency will be:
If a fixed output frequency is desired, i.e. N and f
fixed, then a
Excessively large tracking bandwidth may cause the PLL
to lock on the harmonics of the input signals; and the small
tracking range increases the “lock-up” or acquisition time.
Design Instructions
For a given performance requirement, the circuit of
Figure 12 can be optimized as follows:
a) Choose center frequency, f
f
frequency to be synthesized. If a range of output
max
standard value.
= N
R
or:
R
Calculate R
output swing: Let R
R
0
1
C
max
/R
1
= 80.6k .
= 89.3k .
sets the tracking bandwidth and C
1
10% tracking bandwidth is recommended.
= (3)(0.0746) = 0.224
(f
S
)
max
max
C
0
f
0
and C
and R
and f
can be rounded-off to nearest
and f
f
max
0
/4) = 186pF.
min
F
0
F
min
, set the VCO free running
0
- f
= 100k . Then,
to get
, to be equal to the output
= N
min
, to be synthesized. A
min
(f
4V peak
1
S
is equal to N
)
min
1
S
sets the
= f
S
1
are
/N
fS
.