AS7C1024 ETC, AS7C1024 Datasheet - Page 2

• Manufacturer Part Number: AS7C1024
• Description: 5V/3.3V 128K8 CMOS SRAM (Evolutionary Pinout)
• Manufacturer: ETC

Functional description
The AS7C1024 and AS7C31024 are high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices
organized as 131,072 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple
interfacing are desired.
Equal address access and cycle times (t
are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with
multiple-bank systems.
When CE1 is high or CE2 is low the devices enter standby mode. If inputs are still toggling, the device will consume I
If the bus is static, then full standby power is reached (I
0.33mW under nominal full standby conditions. All devices in this family will retain data when VCC is reduced as low as 2.0V.
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-
I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid
bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable ( OE) or write
enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high.
The chips drive I/O pins with the data word referenced by the input address. When either chip enable is inactive, output
enable is inactive, or write enable is active, output drivers stay in high-impedance mode.
Absolute maximum ratings
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Key: X = Don’t Care, L = Low, H = High
Voltage on V
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with V
DC current into outputs (low)
AS7C1024
AS7C31024
2
CE1
H
X
L
L
L
CC
relative to GND
CE2
H
H
H
X
L
CC
Parameter
applied
WE
X
X
H
H
L
AA
ALLIANCE SEMICONDUCTOR
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
H
X
X
X
L
SB1
AS7C31024
AS7C1024
or I
SB2
). For example, the AS7C31024 is guaranteed not to exceed
®
Symbol
High Z
High Z
High Z
I
T
D
T
V
V
V
OUT
Data
P
D
bias
OUT
stg
t1
t1
t2
D
IN
–0.50
–0.50
-0.50
Min
–65
–55
–
–
Output disable (I
Standby (I
Standby (I
V
CC
Write (
+150
+125
+7.0
+5.0
Read (I
Max
1.0
20
+0.50
OE
Mode
) of 5/6/8/10 ns
SB
SB
ICC
CC
, I
, I
)
)
SB1
SB1
CC
SB
)
)
11/29/00
Unit
)
mA
power.
W
V
V
V
C
C