AS7C1024 ETC, AS7C1024 Datasheet - Page 5
AS7C1024
Manufacturer Part Number
AS7C1024
Description
5V/3.3V 128K8 CMOS SRAM (Evolutionary Pinout)
Manufacturer
ETC
Datasheet
1.AS7C1024.pdf
(9 pages)
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Write cycle (over the operating range)
Shaded areas contain advance information.
Write waveform 1 ( WE controlled)
Write waveform 2 (CE1 and CE2 controlled)
Write cycle time
Chip enable (CE1) to write end
Chip enable (CE2) to write end
Address setup to write end
Address setup time
Write pulse width
Address hold from end of write
Data valid to write end
Data hold time
Write enable to output in high Z
Output active from write end
Address
11/29/00
Address
D
D
OUT
CE1
CE2
OUT
WE
D
D
WE
IN
IN
Parameter
t
AS
t
AS
Symbol
t
t
t
t
t
t
t
t
ALLIANCE SEMICONDUCTOR
CW1
CW2
t
t
t
WC
DW
WZ
OW
AW
WP
DH
AH
AS
t
t
WZ
WZ
Min
10
t
9
9
9
0
7
0
6
0
–
3
AW
t
CW1
t
AW
-10
, t
t
Max
t
WC
t
WP
WC
CW2
–
–
–
–
–
–
–
–
–
5
–
t
WP
Min
t
12
10
10
10
DW
0
8
0
6
0
–
3
Data valid
-12
t
DW
Data valid
®
Max
–
–
–
–
–
–
–
–
–
5
–
Min Max
t
15
12
12
12
AH
0
9
0
9
0
–
3
t
t
DH
OW
-15
–
–
–
–
–
–
–
–
–
5
–
t
t
AH
DH
Min
20
12
12
12
12
10
0
0
0
3
–
-20
Max
–
–
–
–
–
–
–
–
–
5
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AS7C31024
AS7C1024
Notes
4, 5
4, 5
4, 5
12
12
12
5