AM79C985 Advanced Micro Devices, AM79C985 Datasheet
AM79C985
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AM79C985 Summary of contents
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... PRELIMINARY Am79C985 enhanced Integrated Multiport Repeater Plus (eIMR+™) DISTINCTIVE CHARACTERISTICS Repeater functions compliant with IEEE 802.3 Repeater Unit specifications Direct interface with the Am79C987 Hardware Implemented Management Information Base (HIMIB™) device for building a basic managed multiport repeater Full software backwards compatibility with existing hub designs using Integrated Multiport Repeater Plus (IMR+™ ...
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... BLOCK DIAGRAM . Am79C985 20651B-1 ...
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... Am79C985 enhanced Integrated Multiport Repeater Plus (eIMR+) Valid Combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am79C985 Valid Combinations 3 ...
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... PCnet™-PCI Single-Chip Ethernet Controller (for PCI bus) Am79C970A PCnet™-PCI II Full Duplex Single-Chip Ethernet Controller (for PCI bus) Am79C974 PCnet™-SCSI Combination Ethernet and SCSI Controller for PCI Systems . Description Am79C985 ...
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... Management Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 eIMR+ /HIMIB Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Management Port Interface Command/Response Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Port Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Management Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SET (Write Commands Get (Read Commands SYSTEMS APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 eIMR Port Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Twisted Pair Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Twisted Pair Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Am79C985 5 ...
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... IMR+ Mode External Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Visual Status Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DC CHARACTERISTICS over Commercial operating ranges unless otherwise specifi SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 KEY TO SWITCHING WAVEFORMS SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 SWITCHING TEST CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 APPENDIX A - SECURITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A Am79C985 ...
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... eIMR+ Am79C985 Am79C985 LDC2 LDC1 73 72 LDC0 71 VDD 70 LDGB 69 LDGA 68 LDB4 67 DVSS 66 LDA4 65 LDB3 64 LDA3 63 DVSS 62 LDB2 61 LDA2 ...
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... Am79C985 Am79C985 VDD LDC2 LDC1 LDC0 VDD LDGB LDGA LDB4 DVSS LDA4 LDB3 LDA3 DVSS LDB2 LDA2 VDD LDB1 LDA1 NC DVSS LDB0 LDA0 ACT7 ACT6 ...
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... DO– DI+ SI DI– Am79C985 SO CI+ CI– SCLK AMODE LDA[4:0], LDB[4:0] STR LDGA, LDGB CRS_I LDC[2:0] CRS ACT[7:0] SI_D CLK RST AUI Repeater Expansion State Machine Twisted Pair Am79C985 Twisted Pair Ports (4 Ports) AUI LED Interface 20651B-4 Port Port 3 20651B-5 9 ...
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... COL 55 35 DVSS 56 36 ACK 57 37 DAT 58 38 VDD 59 39 JAM 60 40 CRS 61 41 DVSS Am79C985 Pin Name Pin No. Pin Name SO 64 LDA3 SCLK 65 LDB3 VDD 66 LDA4 ACT0 67 DVSS ACT1 68 LDB4 ACT2 69 LDGA DVSS 70 LDGB ACT3 71 VDD ACT4 ...
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... SCLK 67 43 VDD 68 44 ACT0 69 45 ACT1 70 46 ACT2 71 47 DVSS 72 48 ACT3 73 49 ACT4 74 50 ACT5 75 Am79C985 Pin Name Pin No. Pin Name ACT6 76 LDC2 ACT7 80 VDD LDA0 81 TXD0+ LDB0 82 TXD0- DVSS 83 AVSS NC 84 TXD1+ ...
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... Input/Output, Active LOW, Open Drain When asserted, COL indicates that more than one eIMR+ device is active. Each eIMR+ device generates the Collision Jam sequence independently. When the eIMR+ device is configured for Internal Arbitration Am79C985 or SELI is driven by SELO from 0 1 selects between ...
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... The HIMIB device uses this input to communicate with the eIMR+ device. STR connects to an internal pull-up resistor. The resistance value is sufficiently high to allow the STR pins of two eIMR+ devices to be connected together without presenting an excessive load to the HIMIB device. Am79C985 Two eIMR+ Devices Single Primary Secondary eIMR+ ...
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... This pin supplies power to the device. AVSS Analog Ground Ground Pin This pin is the ground reference for the differential receivers and drivers. DVSS Digital Ground Ground Pin This pin is the ground reference for all the digital logic in the eIMR+ device. Am79C985 , SI, and 0-1 ...
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... FUNCTIONAL DESCRIPTION The Am79C985 eIMR+ device is a single-chip imple- mentation of an IEEE 802.3/Ethernet repeater (or hub offered with four integral 10BASE-T ports plus one RAUI port comprising the basic repeater. The eIMR+ device is also expandable, enabling the implementation of high port count repeaters based on several eIMR+ devices. The eIMR+ device interfaces directly with AMD’ ...
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... Proper termination is shown in the Systems Applica- tions section. Table 1. eIMR+ States after Reset State after Reset HIGH LOW HIGH HIGH IMPEDANCE IDLE ENABLED STANDARD ALGORITHM STANDARD ALGORITHM ENABLED, TP PORTS IN LINK FAIL DISABLED IF SI PIN IS HIGH ENABLED IF SI PIN IS LOW Am79C985 Pull Up/Pull Down Either No Terminated N/A N/A N/A N/A ...
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... Table 2 with a blink period specified next to it at- tribute has no blink period specified, the LED indicates the attribute by being solidly lit. Am79C985 , and 0-4 and LDB repre- ...
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... LB remains latched until carrier sense is sampled again for the next packet. The default/power-up state for LB is false (off). Figure 1 shows the recommended connection of LEDs. When LDA LED lights. eIMR+ LED Interface Figure 1. Visual Monitoring Application—Direct Am79C985 AUI LEDs LDB LDA 1-4 0 PAR LB CRS LB ...
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... Table 3. Network Utilization represents 0 Number of LEDs Lit by ACT Figure 2. Network Activity Display latch data; update display; clear counter next counting cycle counter is active Figure 3. Activity Sampling Am79C985 Percentage Utilization 0-7 >80% >64% >32% >16% >8% >4% >2% > 20651B-7 20651A-7 20651B-8 19 ...
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... When ACK is HIGH, DAT and JAM are in the high-impedance state. DAT and JAM go active when ACK goes LOW. Refer to the Systems Applica- tions section (Fig.14) for the configuration of IMR+ mode of operation. Note: The IMR+ mode is recommended when arbitrating between multiple boards. Am79C985 + SELI ))+ 1 0 & SELI ) ...
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... If the latter method is used, 20 SCLK clock transitions are required for management com- mands that produce SO data, and 14 SCLK clock tran- sitions are required for management commands that do not produce SO data. Am79C985 SELI_0 SELO SELI_1 20651B-10 21 ...
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... SI_D SO SCLK SI SCLK SI SO CRS a) One eIMR Device Connected to a HIMIB Port & TP[7:4] AUI Port & TP[3: CRS CRS_I eIMR+ eIMR+ (Primary) (Secondary) SO SI_D SCLK SI b) Two eIMR Devices Connected to a HIMIB Figure 6. eIMR-to-HIMIB Connection Am79C985 CRS SO SCLK SI 20651B-11 ...
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... TP ports (TP4-TP7). The status of the AUI port of the secondary device is not retransmitted (see Figure 8). Single eIMR+ Device Primary eIMR+ Device Am79C985 Two eIMR+ Devices Secondary eIMR+ Device 20651B-12 23 ...
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... Programmable Option— CSA AUI Partitioning Algorithm TP Partitioning Algorithm AUI/TP Port Link Test Link Pulse Automatic Receiver Polarity Reversal Extended Distance Mode Blink Rate Software Override of LEDs Am79C985 20651B-13 Off Normal Normal Enabled Enabled Enabled State reset Disabled Off Disabled ...
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... PBSL 0000 1000 1001 PBSL 0000 1000 0000 0000 C3..C0 1010 0000 0000 E3..E0 1101 0000 0000 L3..L0 1110 0000 0000 P3..P0 1111 0000 M000 0000 1111 1111 0000 0011 Am79C985 SO Data SO Data Primary Secondary 0000 PBSL PBSL PBSL P S 0000 PBSL PBSL PBSL P S 0000 PBSL ...
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... When enabled, the secondary AUI port is fully func- tional, and can be controlled by the serial/management interface. However, when used with the Am79C987 de- vice, no status is displayed for this port since the HIMIB device does not manage this port. At reset, this port is enabled. Am79C985 0010 1111 None None 0010 1110 None ...
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... The state of Automatic Polarity Reversal function is set reset HIGH at the rising edge of RST, the eIMR+ device disables Automatic Polarity Reversal LOW at the rising edge of RST, the eIMR+ device enables Automatic Polarity Reversal. Am79C985 0100 1### None None 0101 1### ...
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... LOW and ‘off’ at the rate set by the Software Override Blink Rate command. Enable Software Override of Bank A LEDs references the blink rate last issued, and overrides any other attribute specified by LDC ware override of LEDs is disabled after reset. Am79C985 1001 #### None None Port(s) affected ...
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... Alternate 2: S and L are not cleared Cleared SI Data SO Data (Sec) SO Data (Pri) SO Data (Single) Alternate 3: None and L are Cleared SI Data SO Data (Sec Data (Pri) SO Data (Single) Am79C985 P ) indicates the statistics of the P ) indicates S 1000 1011 PBSL PBSL P S 0000 PBSL ...
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... If two eIMR+ devices are con- nected together, the secondary device will indicate the version of the primary device in the upper four bits of the SO byte, and its own version number in the lower four bits. Am79C985 1110 0000 0000 P3......P0, P7.....P0 (output to HIMIB) 0000 P7......P4 0000 P3 ...
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... TXD1– 1:1 RXD1+ 100 RXD1– TP Connector 1:1 TXD2+ 110 TXD2– 1:1 RXD2+ 100 RXD2– TP Connector 1:1 TXD3+ 110 TXD3– 1:1 RXD3+ 100 RXD3– 1:1 Figure 10. TXD Termination Am79C985 resistor and a 1:1 transformer. The load is a 20651B-14 Twisted Pair 100 20650A-13 20651B-15 31 ...
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... The IMR+ mode maintains the full functionality of AMD’s IMR+ (Am79C981) device’s expansion bus. In this mode, the eIMR+ device requires external circuitry to The DAT and handle arbitration for control of the bus. Figure 14 shows the configuration for the IMR+ mode of operation. Am79C985 Twisted Pair 100 20650A-14 20650A-14 20651B-16 ...
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... RST CLK eIMR SELI_0 SELI_1 RST SELO CLK eIMR+ SELI_0 SELO SELI_1 DAT JAM ACK COL COL ACK SEL1 SEL2 SEL3 Arbiter Am79C985 eIMR+ SELO 20651B-18 eIMR+ SELI_0 SELO SELI_1 DAT JAM ACK COL GCOL 20651B-19 ...
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... LEDs. The open drain output of these drivers facilitate this configuration. Refer to Figure 15 LDA[4:0] eIMR+ LDB[4:0] LDA[4:0] eIMR+ LDB[4:0] Figure 15. Visual Status Display Connection Am79C985 VDD LDGA LDGB LDGA LDGB 20651B-20 ...
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... 5 – (Note (Note <V < (Note 5 Am79C985 ) . . . . . . . . . . . . . . . . .+ Min Max Unit –0.5 0.8 V 2.0 0 – 0.4 V 2.4 – V – – – 0.4 V –500 500 A V – 3.0 V – 1.0 V ...
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... Sinusoid 5 MHz<f<10 MHz Sinusoid 5 MHz<f<10 MHz Sinusoid 5 MHz<f<10 MHz Sinusoid 5 MHz<f<10 MHz Sinusoid 5 MHz<f<10 MHz Sinusoid 5 MHz<f<10 MHz (Note 1) CLK = 20 MHz V = +5.25V DD CLK = 20 MHz V = +5.25V DD Am79C985 Min Max Unit 300 520 mV –520 –300 mV 150 293 mV –293 –150 mV 180 365 mV –365 –180 ...
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... IN ASQ |V |>|V | (Note 3) IN ASQ |V |>|V | (Note 4) IN ASQ |V |>|V | (Note 5) IN ASQ 100 100 pF L Am79C985 Min Max Unit 49.995 50.005 – – 150 – – – – ...
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... Test Conditions |V |>|V | (Note 6) IN THS C = 100 100 pF L (max) will turn internal DI carrier sense on. PWODI (max) will turn internal CI carrier sense on. PWOCI Am79C985 Min Max Unit – 250 375 ns 136 200 120 ...
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... May Will be Change Changing from from Don’t Care, Changing, Any Change State Permitted Unknown Does Not Center Apply Line is High- Impedance “Off” State t CLK t CLKH t CLKL t CLKF CLKR Figure 16. Clock Timing Am79C985 KS000010-PAL 20650A-20 20651B-21 39 ...
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... AMODE, SELI[0], SI_D, CRS_I RST SCLK t t SCLKH SCLKL t t SISET SODLY Figure 17. Management Port Timing t RSTHLD t RST or t PRST Figure 18. Reset Timing t XRS Figure 19. Mode Initialization Am79C985 t SCLKR t SCLKF t SIHLD 20651B-22 t RSTSET 20651B-23 t XRH 20651B-24 ...
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... TCLK SELO ACK COL DAT/JAM Note: TCLK represents internal eIMR+ timing DJSET IN Figure 20. Expansion Bus Input Timing t t CLKHRH CLKHRL t CASET t CAHLD t CLKHDR OUT Figure 21. Expansion Bus Output Timing Am79C985 t DJHOLD 20651B-25 t CASET t CLKHDZ 20651B-26 41 ...
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... CLK D0+ D0- t PWKDI (t PWKCI DI+ ( ASQ t PWODI (t ) PWOCI CLKHRH t CASET t CLKHRL t CASET DOTD DOTR DOTF Figure 23. AUI Timing Diagram (t ) Figure 24. AUI Receive Diagram Am79C985 t CAHLD IN 20651A-27 20651B-27 20651A-27 t DOETD 20651B-28 t PWKDI ) PWKCI 20650A-28 20651B-29 ...
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... PWLP V TSQ+ RXD+/– V TSQ– t PWKRD PERLP Figure 26. TP Idle Link Test Pulse t PWKRD Figure 27. TP Receive Timing Diagram Am79C985 1 0 ETD t TETD 20651B-30 20651B-31 t PWKRD V THS+ V THS– 20560A-31 20651B-32 43 ...
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... SWITCHING TEST CIRCUIT Pin Test Point V SS Figure 28. Switching Test Circuit Am79C985 20651B-33 20650A-32 ...
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... Pin 1 I.D. 1.185 1.195 1.150 1.156 .026 .050 REF .032 TOP VIEW .062 .083 .042 .056 .007 .013 .090 .130 .165 .180 SIDE VIEW Am79C985 1.090 1.130 1.000 REF .013 .021 SEATING PLANE 16-038-SQ PL 084 DF79 8-1- ...
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... PQR100 100-Pin Plastic Quad Flat Pack Pin 100 12.35 REF Pin 1 I.D. Pin 30 2.70 2.90 0.25 MIN 17.00 17.40 13.90 14.10 18.85 REF Pin 50 0.65 BASIC Am79C985 Pin 80 19.90 20.10 23.00 23.40 3.35 MAX SEATING PLANE 16-038-PQR-1_AH PQR100 DP92 6-20-96 lv ...
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... The eIMR+/HIMIB devices can determine if there is a match on the repeater by monitoring its ports and by monitoring signals on the eIMR+/HIMIB expan- sion bus. AUI TP0 TP1 TP2 TP3 TP4 Am79C985 TP5 TP6 TP7 20651B-34 A-1 ...
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... Hardware Implemented Management Information Base (HIMIB), Integrated Multiport Repeater (IMR) Integrated Multiport Repeater Plus (IMR+), Basic Integrated Multiport Repeater (bIMR), and enhanced Multiport Repeater Plus (eIMR+) are trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. A-2 Am79C985 ...