AM79C985 Advanced Micro Devices, AM79C985 Datasheet - Page 13

• Manufacturer Part Number: AM79C985
• Description: enhanced Integrated Multiport Repeater Plus (eIMR+)
• Manufacturer: Advanced Micro Devices

mode, COL is an I/O and must be pulled to VDD via a
minimum equivalent resistance of 1 k
eIMR+ device expansion port is configured for IMR+
mode, COL is an input driven by an external arbiter.
Management Port
AMODE
AUI Mode
Input
At reset, this pin sets the AUI port to either normal or
reversed mode. If AMODE is LOW at the rising edge of
RST, the AUI port is set to the normal mode; if AMODE
is HIGH, the AUI port is set to the reversed mode.
CRS
Carrier Sense
Output
The states of the internal carrier-sense signals for the
AUI port and the four twisted-pair ports are output con-
tinuously on this pin. The output is a serial bit stream
synchronized to CLK. When two eIMR+ devices share
a common HIMIB device, CRS on the first device must
be connected to the CRS_I (input) of the second eIMR+
device.
CRS_I
Carrier Sense In
Input
CRS_I is used when two eIMR+ devices share a com-
mon HIMIB device. The CRS output from the first eIMR+
should be input to the second eIMR+ via this pin. Inter-
nally, the second eIMR+ appends the information on
CRS_I to its own carrier-sense information and outputs
the combined result to the HIMIB chip via its CRS pin.
At the rising edge of RST, CRS_I is used to set the
eIMR+ device’s management mode. CRS_I HIGH indi-
cates that only a single eIMR+ device is connected to
the HIMIB chip. CRS_I LOW indicates that two eIMR+
devices are connected to a HIMIB chip.
SCLK
Serial Clock In
Input
Serial data (input or output) is clocked (in or out) on the
rising edge of the signal on this pin. SCLK is asynchro-
nous to CLK and can operate at frequencies up to 10
MHz.
SI
Serial In
Input
The SI pin is used as a test/management serial input
port. Management commands are clocked in on this pin
synchronous to the SCLK input.
At reset, SI sets the state of the Automatic Polarity Re-
versal function. If SI is HIGH at the rising edge of RST,
P R E L I M I N A R Y
When the
Am79C985
Automatic Polarity Reversal is disabled. If SI is LOW at
the rising edge of RST, Automatic Polarity Reversal is
enabled.
SI_D
Serial Input Append
Input
SI_D is used when two eIMR+ devices share a common
HIMIB device. The SO output from the first eIMR+ de-
vice should be input to the second eIMR+ chip via this
pin. Internally, the second eIMR+ chip appends the
SI_D data to its own serial data stream and outputs the
result to the HIMIB device via its SO pin.
When two eIMR+ devices are connected to a HIMIB
device, the HIMIB device has attribute counters for the
AUI port on only one of the eIMR+ devices. That eIMR+
device is referred to as the primary eIMR+ device. The
other device is referred to as the secondary eIMR+ de-
vice.
At the rising edge of RST, the combination of CRS_I
and SI_D is used to set the eIMR+ device’s manage-
ment mode. If CRS_I is HIGH, the state of SI_D is ig-
nored and the eIMR+ device is configured as a single
eIMR+. If CRS_I is LOW, SI_D HIGH indicates that the
eIMR+ device is the secondary device. If CRS_I is LOW
and SI_D is LOW, the eIMR+ device is configured as
the primary device.
SO
Serial Out
Output
The SO pin is used as a management command serial
output port. Responses to management commands are
clocked out on this pin synchronous to the SCLK input.
STR
Store
Input
The HIMIB device uses this input to communicate with
the eIMR+ device. STR connects to an internal pull-up
resistor. The resistance value is sufficiently high to allow
the STR pins of two eIMR+ devices to be connected
together without presenting an excessive load to the
HIMIB device.
CRS_I
0
0
1
1
SI_D
0
1
0
1
Device
Single
eIMR+
Primary
Device
eIMR+
Two eIMR+ Devices
Secondary
Device
eIMR+
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