AM79C985 Advanced Micro Devices, AM79C985 Datasheet - Page 29

• Manufacturer Part Number: AM79C985
• Description: enhanced Integrated Multiport Repeater Plus (eIMR+)
• Manufacturer: Advanced Micro Devices

Enable Software Override of Bank-B LEDs (Per Port -
AUI and TP, Global)
SI Data
SO Data (Pri)
SO Data (Sec)
This command forces the LEDs in Bank B to blink. In-
dividual LEDs and combinations of LEDs can be select-
ed via the lower four bits of the command byte, as
follows.
The designated LED drivers(s) will switch between
LOW and ‘off’ at the rate set by the Software Override
of LED Blink Rate command. Enable Software Override
of Bank B LEDs references the blink rate last issued,
and overrides any other attribute specified by LDC
Software override of LEDs is disabled after reset.
Software Override of LED Blink Rate
SI Data
SO Data (Pri)
SO Data (Sec)
This command sets the blink Period of the LEDs with
Software Override enabled. The duty cycle is 50%. This
command defaults to ‘off’ at reset.
These settings apply to the blink rate for both Bank A
and Bank B. This command must precede the Enable
Software Override of Bank A/B LEDs command. All LED
combinations selected for software override will refer-
ence the blink rate last issued.
Get (Read Commands)
AUI Port(s) Status
SI Data
SO Data (Sec)
SO Data (Pri)
SO Data (Single)
The combined AUI status of the eIMR+ device(s) allows
a single instruction to be used to monitor the AUI port(s).
####
0000-0111 TP0 - TP7
1000
1001
1010
1011
1100
1101
1110
Setting
1110 1000
1110 1001
1110 1010
1110 1011
1100 ####
None
None
Port(s) affected
Primary AUI
Secondary AUI
Both AUI ports
All TP ports
All ports
Primary Global
Secondary Global
1110 1###
None
None
1000 1111
PBSL
0000 PBSL
PBSL 0000
P
PBSL
Blink Period
Off
512 ms
1560 ms
Solid On
S
P R E L I M I N A R Y
0-2
Am79C985
.
The four local status bits are:
P
This bit is ‘0’ if the AUI port is partitioned and ‘1’ if the
AUI port is connected.
B
This bit is set to ‘1’ if there is an instance of FIFO over-
flow or underflow. The bit is cleared when the eIMR+
device is read.
S
This bit is set to ‘1’ if the SQE test error is detected by
the eIMR+ chip. The bit is cleared when the status is
read.
L
The MAU attached to the AUI port is required to loop-
back data transmitted to DO onto the DI circuit. If the
loopback carrier is not detected by the eIMR+ device,
this bit is set to ‘1’. This bit is cleared when the status
is read.
If a single eIMR+ device is connected to a HIMIB device,
SO is PBSL 0000. If two eIMR+ devices are connected
to a HIMIB device, SO on the primary device is 0000
PBSL
PBSL
primary eIMR+ device and the subscript (
the statistics of the secondary eIMR+ device.
Alternate AUI Port(s) Status
There are three further variations of the AUI Port Status
Command allowing selective clearing of a combination
of B,S, and L bits. These are the following:
Alternate 1: B is not cleared, S and L are Cleared
SI Data
SO Data (Sec)
SO Data (Pri)
SO Data (Single)
Alternate 2: S and L are not cleared, B is Cleared
SI Data
SO Data (Sec)
SO Data (Pri)
SO Data (Single)
Alternate 3: None of S, B, and L are Cleared
SI Data
SO Data (Sec)
SO Data (Pri)
SO Data (Single)
P
S
, and SO on the secondary device is PBSL
. The subscript (
Partitioning Status
Bit Rate Error
SQE Test Status
Loopback Error
P
) indicates the statistics of the
1000 1011
PBSL
0000 PBSL
PBSL 0000
1000 1101
PBSL
0000 PBSL
PBSL 0000
1000 1001
PBSL
0000 PBSL
PBSL 0000
P
P
P
PBSL
PBSL
PBSL
S
S
S
S
) indicates
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P