K4S643232E- Samsung semiconductor, K4S643232E- Datasheet - Page 5

• Manufacturer Part Number: K4S643232E-
• Description: 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL(3.3V)
• Manufacturer: Samsung semiconductor

K4S643232E-TE/N
PIN FUNCTION DESCRIPTION
CLK
CS
CKE
A
BA0,1
RAS
CAS
WE
DQM0 ~ 3
DQ
V
V
NC
0
DD
DDQ
~ A
0
/V
Pin
~
/V
SS
10
31
SSQ
System clock
Chip select
Clock enable
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
Data input/output
Power supply/ground
Data output power/ground
No Connection
Name
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.
Row/column addresses are multiplexed on the same pins.
Row address : RA
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No connection on the device.
0
- 5 -
~ RA
10
SHZ
, Column address : CA
after the clock and masks the output.
Input Function
0
~ CA
7
CMOS SDRAM
Rev. 1.4 (Dec. 2001)