K4S643232E-TI60 Samsung semiconductor, K4S643232E-TI60 Datasheet - Page 10

• Manufacturer Part Number: K4S643232E-TI60
• Description: 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL
• Manufacturer: Samsung semiconductor

K4S643232E-TI/P
SIMPLIFIED TRUTH TABLE
Notes :
Register
Refresh
Bank active & row addr.
Read &
column address
Write &
column address
Burst Stop
Precharge
Clock suspend or
active power down
Precharge power down mode
DQM
No operation command
1. OP Code : Operand code
2. MRS can be issued only at all banks precharge state.
3. Auto refresh functions are as same as CBR refresh of DRAM.
4. BA
5. During burst read or write with auto precharge, new read/write command can not be issued.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
A
A new command can be issued after 2 CLK cycles of MRS.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
If both BA
If both BA
If both BA
If both BA
If A
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
0
0
~ A
10
~ BA
/AP is "High" at row precharge, BA
10
Command
& BA
1
0
0
0
0
Mode register set
Auto refresh
Self
refresh
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
Bank selection
All banks
: Bank select addresses.
and BA
is "Low" and BA
is "High" and BA
and BA
0
~ BA
1
1
are "Low" at read, write, row active and precharge, bank A is selected.
are "High" at read, write, row active and precharge, bank D is selected.
1
: Program keys. (@ MRS)
Entry
Entry
Entry
Exit
Exit
Exit
1
1
is "High" at read, write, row active and precharge, bank B is selected.
is "Low" at read, write, row active and precharge, bank C is selected.
CKEn-1
H
H
H
H
H
H
H
H
H
H
H
L
L
L
0
and BA
CKEn
H
H
H
H
X
X
X
X
X
X
X
L
L
L
1
is ignored and all banks are selected.
CS
H
H
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
RP
- 10
after the end of burst.
RAS
H
X
H
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
X
CAS
H
H
H
H
H
H
X
X
V
X
X
X
V
X
L
L
L
L
(V=Valid, X=Don t care, H=Logic high, L=Logic low)
WE
H
H
X
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
DQM
X
X
X
X
X
X
X
X
X
X
X
X
V
X
BA
V
V
V
V
X
0,1
CMOS SDRAM
Rev. 1.2 (Oct. 2001)
A
OP code
10
Row address
H
H
H
L
L
L
/AP
X
X
X
X
X
X
X
A
(A
(A
Column
address
Column
address
9
0
0
X
~ A
~ A
~ A
,
7
7
0
)
)
Note
1,2
4,5
4,5
3
3
3
3
4
4
6
7