K4H560838F-UCC4 Samsung semiconductor, K4H560838F-UCC4 Datasheet - Page 12

• Manufacturer Part Number: K4H560838F-UCC4
• Description: 256Mb F-die DDR400 SDRAM Specification
• Manufacturer: Samsung semiconductor

< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs change logic state once per Deselect cycle.
2. Timing patterns
IDD7A : Operating current: Four bank operation
1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on Deselet edge are not changing.
2. Timing patterns
DDR SDRAM 256Mb F-die (x8, x16)
- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK
- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK
Iout = 0mA
Setup : A0 N N R0 N N N N P0 N N
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
Iout = 1mA
Setup : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N - repeat the same timing with random address changing
Legend : A = Activate, R=Read, W=Write, P=Precharge, N=NOP
*50% of data changing at every transfer
*50% of data changing at every transfer
Rev. 1.1 August. 2003
DDR SDRAM