K6T1008C2E-B Samsung semiconductor, K6T1008C2E-B Datasheet
K6T1008C2E-B
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K6T1008C2E-B Summary of contents
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... K6T1008C2E Family Document Title 128Kx8 bit Low Power CMOS Static RAM Revision History Revision No. History 0.0 Design target 1.0 Finalize - Improve t form 55ns to 50ns for 70ns product Remove 55ns speed bin from industrial product. 1.01 Errata correction 2.0 Revise 3.0 Revise - Add 55ns parts to industrial products. ...
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... Power Supply Voltage: 4.5~5.5V Low Data Retention Voltage: 2V(Min) Three state output and TTL Compatible Package Type: 32-DIP-600, 32-SOP-525, 32-TSOP1-0820F/R PRODUCT FAMILY Product Family Operating Temperature K6T1008C2E-L Commercial(0~70 C) K6T1008C2E-B K6T1008C2E-P Industrial(-40~85 C) K6T1008C2E-F 1. The parameters are tested with 50pF test load PIN DESCRIPTION A11 ...
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... K6T1008C2E Family PRODUCT LIST Commercial Temperature Products(0~70 C) Part Name K6T1008C2E-DL55 32-DIP, 55ns, Low Power K6T1008C2E-DL70 32-DIP, 70ns, Low Power K6T1008C2E-DB55 32-DIP, 55ns, Low Low Power K6T1008C2E-DB70 32-DIP, 70ns, Low Low Power K6T1008C2E-GL55 32-SOP, 55ns, Low Power K6T1008C2E-GL70 32-SOP, 70ns, Low Power ...
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... Output high voltage V OH Standby Current(TTL Standby Current(CMOS) I SB1 for Low power product, in case of Low Low power products are comercial=10 A, industrial= Product K6T1008C2E Family All Family K6T1008C2E Family K6T1008C2E Family Symbol Test Condition Test Conditions V ...
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... WHZ Test Condition 1) CS Vcc-0.2V 1 K6T1008C2E-L K6T1008C2E-B 1) Vcc=3.0V, CS Vcc-0.2V 1 K6T1008C2E-P K6T1008C2F-F See data retention waveform 0.2V(CS controlled CMOS SRAM =- Speed Bins Units 55ns 70ns Max Min Max - ...
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... K6T1008C2E Family TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address Data Out Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) Address High-Z Data out NOTES (READ CYCLE and are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage ...
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... K6T1008C2E Family TIMING WAVEFORM OF WRITE CYCLE(1) Address Data in Data Undefined Data out TIMING WAVEFORM OF WRITE CYCLE(2) Address Data in Data out (WE Controlled CW( CW(2) t WP(1) t AS( Data Valid t WHZ (CS Controlled CW(2) AS( WP( Data Valid ...
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... K6T1008C2E Family TIMING WAVEFORM OF WRITE CYCLE(3) Address Data in Data out NOTES (WRITE CYCLE write occurs during the overlap of a low CS CS going high and WE going low: A write end at the earliest transition among measured from the begining of write to the end of write. ...
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... K6T1008C2E Family PACKAGE DIMENSIONS 32 DUAL INLINE PACKAGE (600mil) #32 13.60 0.20 0.535 0.008 #1 1. 0.075 32 PLASTIC SMALL OUTLINE PACKAGE (525mil) #32 #1 20.87 0.822 20.47 0.806 +0.100 0.41 -0.050 0. +0.004 0.016 0.028 -0.002 42.31 MAX 1.666 41.91 0.20 1.650 0.008 0.46 0.10 0.018 0.004 1.52 2.54 0.10 0.060 0.100 0.004 #17 14.12 0.30 0.556 0.012 #16 2.74 0.20 MAX 0.108 0.008 3.00 0.118 0.20 0.008 1 ...
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... K6T1008C2E Family PACKAGE DIMENSIONS 32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F) +0.10 0.20 -0.05 +0.004 0.008 -0.002 #1 0.50 0.0197 #16 0.25 TYP 0.010 0~8 0.45 ~0.75 0.018 ~0.030 32 THIN SMALL OUTLINE PACKAGE TYPE I (0820R) +0.10 0.20 -0.05 +0.004 0.008 -0.002 #16 0.50 0.0197 #1 0.25 TYP 0.010 0~8 0.45 ~0.75 0.018 ~0.030 20.00 0.20 0.787 0.008 18.40 0.10 0.724 0.004 20.00 0.20 0.787 0.008 18.40 0.10 0.724 0.004 ...