ADIS16136/PCBZ AD [Analog Devices], ADIS16136/PCBZ Datasheet - Page 12

• Manufacturer Part Number: ADIS16136/PCBZ
• Manufacturer: AD [Analog Devices]

AVERAGING/DECIMATION FILTER
The DEC_RATE register (see Table 18) provides user control
for the final filter stage (see Figure 18), which averages and
decimates the output data. For systems that value lower sample
rates, this filter stage provides an opportunity to lower the sample
rate while maintaining optimal bias stability performance. The
−3 dB bandwidth of this filter stage is approximately one half
the output data rate. For example, set DEC_RATE[7:0] = 0x04
(DIN = 0xA204) to reduce the sample rate by a factor of 16.
ADIS16136
MEMS
GYRO
–3dB BANDWIDTH = 380Hz
410Hz
f
SP ≥ 15
SP = SMPL_PRD
S
=
32,768
SP + 1
1595Hz
Figure 18. Sampling and Frequency Response Block Diagram
CLOCK
CLKIN
f
S
Rev. A | Page 12 of 20
B = AVG_CNT[2:0]
N
N
NT = TOTAL NUMBER OF TAPS
B
T
= 2N
= 2
B
B
– 1
When the factory default 1024 SPS sample rate is used, this
decimation setting reduces the output data rate to 64 SPS and
the sensor bandwidth to approximately 32 Hz.
Table 18. DEC_RATE Bit Descriptions
Bits
[15:5]
[4:0]
Description (Default = 0x0000)
Don’t care
Binary; D variable in Figure 18; maximum = 10000 (16)
D = DEC_RATE[4:0]
N
N
N
D
D
D
= 2
= NUMBER OF TAPS
= DATA RATE DIVISOR
D
÷N
D
Data Sheet