IS43DR16320B25DBL

Manufacturer Part NumberIS43DR16320B25DBL
DescriptionBGA84
ManufacturerIntegrated Silicon Solution
IS43DR16320B25DBL datasheet
 


Specifications of IS43DR16320B25DBL

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IS43/46DR86400B, IS43/46DR16320B  
512Mb (x8, x16) DDR2 SDRAM
FEATURES 
Clock frequency up to 400MHz 
Posted CAS 
Programmable CAS Latency: 3, 4, 5 and 6 
Programmable Additive Latency: 0, 1, 2, 3, 4 and 5 
Write Latency = Read Latency‐1 
Programmable Burst Sequence: Sequential or 
Interleave 
Programmable Burst Length: 4 and 8 
Automatic and Controlled Precharge Command 
Power Down Mode 
Auto Refresh and Self Refresh 
Refresh Interval: 7.8 s (8192 cycles/64 ms) 
OCD (Off‐Chip Driver Impedance Adjustment) 
ODT (On‐Die Termination) 
Weak Strength Data‐Output Driver Option 
Bidirectional differential Data Strobe (Single‐
ended data‐strobe is an optional feature) 
OPTIONS   
 
 Configuration: 
64Mx8 (16M x 8 x 4 banks) 
32Mx16 (8M x 16 x 4 banks)  
 Package: 
60‐ball TW‐BGA  for x8 
84‐ball TW‐BGA for x16 
Clock Cycle Timing 
 
‐5B 
 Speed Grade 
DDR2‐400B 
CL‐tRCD‐tRP 
3‐3‐3 
tCK (CL=3) 
tCK (CL=4) 
tCK (CL=5) 
tCK (CL=6) 
Frequency (max) 
200 
Note: The ‐5B device specification is shown for reference only. 
 
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
 
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
 
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
 
 
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. H, 11/30/2011
On‐Chip DLL aligns DQ and DQs transitions with 
CK transitions 
Differential clock inputs CK and CK# 
VDD and VDDQ = 1.8V ± 0.1V 
PASR (Partial Array Self Refresh) 
SSTL_18 interface 
tRAS lockout supported 
Read Data Strobe supported (x8 only) 
Internal four bank operations with single pulsed 
RAS 
Operating temperature: 
Commercial (T
Industrial (T
Automotive, A1 (T
+95°C) 
Automotive, A2 (T
to +105°C) 
ADDRESS TABLE 
Parameter
Row  Addressing
Column Addressing
Bank Addressing
Precharge Addressing
‐37C 
‐3D 
DDR2‐533C 
DDR2‐667D 
4‐4‐4 
5‐5‐5 
3.75 
3.75 
3.75 
3.75 
266 
333 
DECEMBER 2011
= 0°C to +70°C ; T
= 0°C to +85°C) 
= ‐40°C to +85°C; T
= ‐40°C to +95°C) 
= ‐40°C to +85°C; T
= ‐40°C to 
= ‐40°C to +105°C; T
= ‐40°C 
64Mx8 
32Mx16
A0‐A13 
A0‐A12
A0‐A9 
A0‐A9
BA0‐BA1 
BA0‐BA1
A10 
A10
‐25E 
‐25D 
DDR2‐800E 
DDR2‐800D 
6‐6‐6 
5‐5‐5 
3.75 
3.75 
2.5 
2.5 
2.5 
400 
400 
Units 
 
tCK 
ns 
ns 
ns 
ns 
MHz 
1