S3C44B0X

Manufacturer Part NumberS3C44B0X
DescriptionBGA
ManufacturerSamsung
S3C44B0X datasheets
 


Specifications of S3C44B0X

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UART
UART FIFO CONTROL REGISTER
There are two UART FIFO control registers, UFCON0 and UFCON1, in the UART block.
Register
Address
UFCON0
0x15000008
UFCON1
0x15004008
UFCONn
Bit
Tx FIFO Trigger
[7:6]
These two bits determine the trigger level of transmit FIFO.
Level
00 = Empty
10 = 8-byte
Rx FIFO Trigger
[5:4]
These two bits determine the trigger level of receive FIFO.
Level
00 = 4-byte
10 = 12-byte
Reserved
[3]
Tx FIFO Reset
[2]
This bit is auto-cleared after resetting FIFO
0 = Normal
Rx FIFO Reset
[1]
This bit is auto-cleared after resetting FIFO
0 = Normal
FIFO Enable
[0]
0 = FIFO disable
NOTE:
When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive
mode with FIFO, the Rx interrupt will be generated (receive time out), and the users should check the FIFO status
and read out the rest.
UART MODEM CONTROL REGISTER
There are two UART MODEM control registers, UMCON0 and UMCON1 in the UART block.
Register
Address
UMCON0
0x1500000C
UMCON1
0x1500400C
UMCONn
Bit
Reserved
[7:5]
These bits must be 0's
AFC (Auto Flow
[4]
0 = Disable
Control)
Reserved
[3:1]
These bits must be 0's
Request to Send
[0]
If AFC bit is enabled, this value will be ignored. In this case the
S3C2400 will control nRTS automatically.
If AFC bit is disabled, nRTS must be controlled by S/W.
0 = 'H' level(Inactivate nRTS)
11-12
R/W
Description
R/W
UART channel 0 FIFO control register
R/W
UART channel 1 FIFO control register
Description
01 = 4-byte
11 = 12-byte
01 = 8-byte
11 = 16-byte
1= Tx FIFO reset
1= Rx FIFO reset
1 = FIFO mode
R/W
Description
R/W
UART channel 0 Modem control register
R/W
UART channel 1 Modem control register
Description
1 = Enable
1 = 'L' level(Activate nRTS)
S3C2400 RISC MICROPROCESSOR
Reset Value
0x0
0x0
Initial State
00
00
0
0
0
0
Reset Value
0x0
0x0
Initial State
00
0
00
0